}
template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(StaticInstPtr<ISA> &_staticInst)
+BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
: staticInst(_staticInst), traceData(NULL)
{
initVars();
fault = NoFault;
// note this is a local, not BaseDynInst::fault
- Fault * trans_fault = xc->translateDataReadReq(req);
+ Fault trans_fault = xc->translateDataReadReq(req);
if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
// It's a valid address to cacheable space. Record key MemReq
* @todo Need to find a way to get the cache block size here.
*/
template <class Impl>
-Fault *
+Fault
BaseDynInst<Impl>::copySrcTranslate(Addr src)
{
MemReqPtr req = new MemReq(src, xc, 64);
req->asid = asid;
// translate to physical address
- Fault * fault = xc->translateDataReadReq(req);
+ Fault fault = xc->translateDataReadReq(req);
if (fault == NoFault) {
xc->copySrcAddr = src;
* @todo Need to find a way to get the cache block size here.
*/
template <class Impl>
-Fault *
+Fault
BaseDynInst<Impl>::copy(Addr dest)
{
uint8_t data[64];
req->asid = asid;
// translate to physical address
- Fault * fault = xc->translateDataWriteReq(req);
+ Fault fault = xc->translateDataWriteReq(req);
if (fault == NoFault) {
Addr dest_addr = req->paddr;
#if 0
template <class Impl>
-Fault *
+Fault
BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
{
- Fault * fault;
+ Fault fault;
// check alignments, even speculative this test should always pass
if ((nbytes & nbytes - 1) != 0 || (addr & nbytes - 1) != 0) {