Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5

[gem5.git] / cpu / base_dyn_inst.cc

diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index b8424f576e22fe23384bdf3868c27957e91c9af9..86314bef1cd74505a8b0d920658507558a58d925 100644 (file)
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2001-2004 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -41,10 +41,8 @@
 #include "mem/mem_req.hh"
 
 #include "cpu/base_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
-#include "cpu/ooo_cpu/ooo_impl.hh"
-#include "cpu/ooo_cpu/ooo_cpu.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/alpha_cpu.hh"
 
 using namespace std;
 
@@ -65,11 +63,6 @@ typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc> my_ha
 my_hash_t thishash;
 #endif
 
-/** This may need to be specific to an implementation. */
-//int BaseDynInst<Impl>::instcount = 0;
-
-//int break_inst = -1;
-
 template <class Impl>
 BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
                                Addr pred_PC, InstSeqNum seq_num,
@@ -86,7 +79,7 @@ BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
 }
 
 template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(StaticInstPtr<ISA> &_staticInst)
+BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
     : staticInst(_staticInst), traceData(NULL)
 {
     initVars();
@@ -120,7 +113,7 @@ BaseDynInst<Impl>::initVars()
     asid = 0;
 
     // Initialize the fault to be unimplemented opcode.
-    fault = Unimplemented_Opcode_Fault;
+    fault = UnimplementedOpcodeFault;
 
     ++instcount;
 
@@ -131,31 +124,11 @@ BaseDynInst<Impl>::initVars()
 template <class Impl>
 BaseDynInst<Impl>::~BaseDynInst()
 {
-/*
-    if (specMemWrite) {
-        // Remove effects of this instruction from speculative memory
-        xc->spec_mem->erase(effAddr);
-    }
-*/
     --instcount;
     DPRINTF(FullCPU, "DynInst: Instruction destroyed.  Instcount=%i\n",
             instcount);
 }
-/*
-template <class Impl>
-FunctionalMemory *
-BaseDynInst<Impl>::getMemory(void)
-{
-    return xc->mem;
-}
 
-template <class Impl>
-IntReg *
-BaseDynInst<Impl>::getIntegerRegs(void)
-{
-    return (spec_mode ? xc->specIntRegFile : xc->regs.intRegFile);
-}
-*/
 template <class Impl>
 void
 BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
@@ -169,12 +142,12 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
     req->asid = asid;
 
     // Prefetches never cause faults.
-    fault = No_Fault;
+    fault = NoFault;
 
     // note this is a local, not BaseDynInst::fault
     Fault trans_fault = xc->translateDataReadReq(req);
 
-    if (trans_fault == No_Fault && !(req->flags & UNCACHEABLE)) {
+    if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
         // It's a valid address to cacheable space.  Record key MemReq
         // parameters so we can generate another one just like it for
         // the timing access without calling translate() again (which
@@ -193,7 +166,7 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
      * Replace the disjoint functional memory with a unified one and remove
      * this hack.
      */
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     req->paddr = req->vaddr;
 #endif
 
@@ -215,7 +188,7 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
 
     fault = xc->translateDataWriteReq(req);
 
-    if (fault == No_Fault && !(req->flags & UNCACHEABLE)) {
+    if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
         // Record key MemReq parameters so we can generate another one
         // just like it for the timing access without calling translate()
         // again (which might mess up the TLB).
@@ -244,7 +217,7 @@ BaseDynInst<Impl>::copySrcTranslate(Addr src)
     // translate to physical address
     Fault fault = xc->translateDataReadReq(req);
 
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         xc->copySrcAddr = src;
         xc->copySrcPhysAddr = req->paddr;
     } else {
@@ -270,7 +243,7 @@ BaseDynInst<Impl>::copy(Addr dest)
     // translate to physical address
     Fault fault = xc->translateDataWriteReq(req);
 
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         Addr dest_addr = req->paddr;
         // Need to read straight from memory since we have more than 8 bytes.
         req->paddr = xc->copySrcPhysAddr;
@@ -319,7 +292,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
 #if 0
         panic("unaligned access. Cycle = %n", curTick);
 #endif
-        return No_Fault;
+        return NoFault;
     }
 
     MemReqPtr req = new MemReq(addr, thread, nbytes);
@@ -330,7 +303,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
 
       case Write:
         fault = spec_mem->write(req, (uint8_t *)p);
-        if (fault != No_Fault)
+        if (fault != NoFault)
             break;
 
         specMemWrite = true;
@@ -352,7 +325,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
         break;
 
       default:
-        fault = Machine_Check_Fault;
+        fault = MachineCheckFault;
         break;
     }
 
@@ -371,8 +344,6 @@ BaseDynInst<Impl>::eaSrcsReady()
     // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
     // stored)
 
-//    StaticInstPtr<ISA> eaInst = staticInst->eaCompInst();
-
     for (int i = 1; i < numSrcRegs(); ++i)
     {
         if (!_readySrcRegIdx[i])
@@ -382,16 +353,11 @@ BaseDynInst<Impl>::eaSrcsReady()
     return true;
 }
 
-// Forward declaration...
+// Forward declaration
 template class BaseDynInst<AlphaSimpleImpl>;
-template class BaseDynInst<OoOImpl>;
 
 template <>
 int
 BaseDynInst<AlphaSimpleImpl>::instcount = 0;
 
-template <>
-int
-BaseDynInst<OoOImpl>::instcount = 0;
-
 #endif // __CPU_BASE_DYN_INST_CC__