class InstRecord;
};
-class BaseInst
-{
-};
+// Forward declaration.
+template <class blah>
+class StaticInstPtr;
template <class Impl>
-class BaseDynInst : public FastAlloc
+class BaseDynInst : public FastAlloc, public RefCounted
{
public:
// Typedef for the CPU.
/// Logical register index type.
typedef typename ISA::RegIndex RegIndex;
/// Integer register index type.
- typedef typename ISA::IntReg IntReg;
+ typedef typename ISA::IntReg IntReg;
enum {
MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
bool threadsyncWait;
/** If the BTB missed. */
- bool btbMissed;
+// bool btbMissed;
+
+ /** The global history of this instruction (branch). */
+// unsigned globalHistory;
/** The thread this instruction is from. */
short threadNumber;
static int instcount;
/** Did this instruction do a spec write? */
- bool specMemWrite;
+// bool specMemWrite;
private:
/** Physical register index of the destination registers of this
/** Returns whether the instruction was predicted taken or not. */
bool predTaken() {
-// DPRINTF(FullCPU, "PC: %08p\n", PC);
-// DPRINTF(FullCPU, "predPC: %08p\n", predPC);
-
return( predPC != (PC + sizeof(MachInst) ) );
}
/** Returns whether the instruction mispredicted. */
bool mispredicted() { return (predPC != nextPC); }
+/*
+ unsigned readGlobalHist() {
+ return globalHistory;
+ }
+
+ void setGlobalHist(unsigned history) {
+ globalHistory = history;
+ }
+*/
+
//
// Instruction types. Forward checks to StaticInst object.
//
/** Sets this instruction as ready to commit. */
void setCanCommit() { canCommit = true; }
+ /** Clears this instruction as being ready to commit. */
+ void clearCanCommit() { canCommit = false; }
+
/** Returns whether or not this instruction is ready to commit. */
bool readyToCommit() const { return canCommit; }
OpClass opClass() const { return staticInst->opClass(); }
/** Returns whether or not the BTB missed. */
- bool btbMiss() const { return btbMissed; }
+// bool btbMiss() const { return btbMissed; }
/** Returns the branch target address. */
Addr branchTarget() const { return staticInst->branchTarget(PC); }
storeSize = sizeof(T);
storeData = data;
- if (specMode)
- specMemWrite = true;
+// if (specMode)
+// specMemWrite = true;
MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);