/*
- * Copyright (c) 2001-2004 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include "base/fast_alloc.hh"
#include "base/trace.hh"
-
-#include "cpu/beta_cpu/comm.hh"
+#include "config/full_system.hh"
#include "cpu/exetrace.hh"
-#include "cpu/full_cpu/bpred_update.hh"
-#include "cpu/full_cpu/op_class.hh"
-#include "cpu/full_cpu/spec_memory.hh"
-#include "cpu/full_cpu/spec_state.hh"
#include "cpu/inst_seq.hh"
+#include "cpu/o3/comm.hh"
#include "cpu/static_inst.hh"
-#include "mem/functional_mem/main_memory.hh"
+#include "encumbered/cpu/full/bpred_update.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "encumbered/cpu/full/spec_memory.hh"
+#include "encumbered/cpu/full/spec_state.hh"
+#include "encumbered/mem/functional/main.hh"
/**
* @file
*/
// Forward declaration.
-template <class ISA>
class StaticInstPtr;
template <class Impl>
// Typedef for the CPU.
typedef typename Impl::FullCPU FullCPU;
- //Typedef to get the ISA.
- typedef typename Impl::ISA ISA;
-
/// Binary machine instruction type.
- typedef typename ISA::MachInst MachInst;
- /// Memory address type.
- typedef typename ISA::Addr Addr;
+ typedef TheISA::MachInst MachInst;
/// Logical register index type.
- typedef typename ISA::RegIndex RegIndex;
+ typedef TheISA::RegIndex RegIndex;
/// Integer register index type.
- typedef typename ISA::IntReg IntReg;
+ typedef TheISA::IntReg IntReg;
enum {
- MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
- MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
+ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
+ MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
};
- StaticInstPtr<ISA> staticInst;
+ /** The static inst used by this dyn inst. */
+ StaticInstPtr staticInst;
////////////////////////////////////////////
//
Fault copySrcTranslate(Addr src);
Fault copy(Addr dest);
- // Probably should be private...
+ /** @todo: Consider making this private. */
public:
/** Is this instruction valid. */
bool valid;
FullCPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
- BaseDynInst(StaticInstPtr<ISA> &_staticInst);
+ BaseDynInst(StaticInstPtr &_staticInst);
/** BaseDynInst destructor. */
~BaseDynInst();
private:
+ /** Function to initialize variables in the constructors. */
void initVars();
public:
*/
bool doneTargCalc() { return false; }
- /** Returns the calculated target of the branch. */
-// Addr readCalcTarg() { return nextPC; }
-
+ /** Returns the next PC. This could be the speculative next PC if it is
+ * called prior to the actual branch target being calculated.
+ */
Addr readNextPC() { return nextPC; }
/** Set the predicted target of this current instruction. */
/** Returns the branch target address. */
Addr branchTarget() const { return staticInst->branchTarget(PC); }
+ /** Number of source registers. */
int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
+
+ /** Number of destination registers. */
int8_t numDestRegs() const { return staticInst->numDestRegs(); }
// the following are used to track physical register usage
return staticInst->srcRegIdx(i);
}
+ /** Returns the result of an integer instruction. */
uint64_t readIntResult() { return instResult.integer; }
+
+ /** Returns the result of a floating point instruction. */
float readFloatResult() { return instResult.fp; }
+
+ /** Returns the result of a floating point (double) instruction. */
double readDoubleResult() { return instResult.dbl; }
//Push to .cc file.
}
}
+ /** Marks a specific register as ready.
+ * @todo: Move this to .cc file.
+ */
void markSrcRegReady(RegIndex src_idx)
{
++readyRegs;
}
}
+ /** Returns if a source register is ready. */
bool isReadySrcRegIdx(int idx) const
{
return this->_readySrcRegIdx[idx];
}
+ /** Sets this instruction as completed. */
void setCompleted() { completed = true; }
+ /** Returns whethe or not this instruction is completed. */
bool isCompleted() const { return completed; }
/** Sets this instruction as ready to issue. */
/** Set the next PC of this instruction (its actual target). */
void setNextPC(uint64_t val) { nextPC = val; }
+ /** Returns the exec context.
+ * @todo: Remove this once the ExecContext is no longer used.
+ */
ExecContext *xcBase() { return xc; }
private:
+ /** Instruction effective address.
+ * @todo: Consider if this is necessary or not.
+ */
Addr instEffAddr;
+ /** Whether or not the effective address calculation is completed.
+ * @todo: Consider if this is necessary or not.
+ */
bool eaCalcDone;
public:
+ /** Sets the effective address. */
void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
+
+ /** Returns the effective address. */
const Addr &getEA() const { return instEffAddr; }
+
+ /** Returns whether or not the eff. addr. calculation has been completed. */
bool doneEACalc() { return eaCalcDone; }
+
+ /** Returns whether or not the eff. addr. source registers are ready. */
bool eaSrcsReady();
+
+ public:
+ /** Load queue index. */
+ int16_t lqIdx;
+
+ /** Store queue index. */
+ int16_t sqIdx;
};
template<class Impl>
// Record key MemReq parameters so we can generate another one
// just like it for the timing access without calling translate()
// again (which might mess up the TLB).
+ // Do I ever really need this? -KTL 3/05
effAddr = req->vaddr;
physEffAddr = req->paddr;
memReqFlags = req->flags;
* Replace the disjoint functional memory with a unified one and remove
* this hack.
*/
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
req->paddr = req->vaddr;
#endif
- if (fault == No_Fault) {
- fault = cpu->read(req, data);
- }
- else {
+ if (fault == NoFault) {
+ fault = cpu->read(req, data, lqIdx);
+ } else {
// Return a fixed value to keep simulation deterministic even
// along misspeculated paths.
data = (T)-1;
traceData->setData(data);
}
- storeSize = sizeof(T);
- storeData = data;
-
MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
req->asid = asid;
* Replace the disjoint functional memory with a unified one and remove
* this hack.
*/
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
req->paddr = req->vaddr;
#endif
- if (fault == No_Fault) {
- fault = cpu->write(req, data);
+ if (fault == NoFault) {
+ fault = cpu->write(req, data, sqIdx);
}
if (res) {
// always return some result to keep misspeculated paths
// (which will ignore faults) deterministic
- *res = (fault == No_Fault) ? req->result : 0;
+ *res = (fault == NoFault) ? req->result : 0;
}
return fault;
projects / gem5.git / blobdiff