add in the files to the SConscript for split caches

[gem5.git] / cpu / exec_context.hh

diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 7409095e27b1b7e20ebcc02dec01f82f2ccfe5e9..6a17951f95bd693473bec2006cf58136026f452b 100644 (file)
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2001-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -26,27 +26,29 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __EXEC_CONTEXT_HH__
-#define __EXEC_CONTEXT_HH__
+#ifndef __CPU_EXEC_CONTEXT_HH__
+#define __CPU_EXEC_CONTEXT_HH__
 
-#include "sim/host.hh"
+#include "config/full_system.hh"
+#include "mem/functional/functional.hh"
 #include "mem/mem_req.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "sim/host.hh"
 #include "sim/serialize.hh"
+#include "targetarch/byte_swap.hh"
 
 // forward declaration: see functional_memory.hh
 class FunctionalMemory;
 class PhysicalMemory;
 class BaseCPU;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 
+#include "sim/system.hh"
 #include "targetarch/alpha_memory.hh"
-class MemoryController;
 
-#include "kern/kernel_stats.hh"
-#include "sim/system.hh"
-#include "sim/sw_context.hh"
+class MemoryController;
+class StaticInstBase;
+namespace Kernel { class Binning; class Statistics; }
 
 #else // !FULL_SYSTEM
 
@@ -104,11 +106,6 @@ class ExecContext
     /// Set the status to Halted.
     void halt();
 
-#ifdef FULL_SYSTEM
-  public:
-    KernelStats kernelStats;
-#endif
-
   public:
     RegFile regs;      // correct-path register context
 
@@ -125,8 +122,7 @@ class ExecContext
     // it belongs.  For full-system mode, this is the system CPU ID.
     int cpu_id;
 
-#ifdef FULL_SYSTEM
-
+#if FULL_SYSTEM
     FunctionalMemory *mem;
     AlphaITB *itb;
     AlphaDTB *dtb;
@@ -135,10 +131,15 @@ class ExecContext
     // the following two fields are redundant, since we can always
     // look them up through the system pointer, but we'll leave them
     // here for now for convenience
-    MemoryController *memCtrl;
+    MemoryController *memctrl;
     PhysicalMemory *physmem;
 
-    SWContext *swCtx;
+    Kernel::Binning *kernelBinning;
+    Kernel::Statistics *kernelStats;
+    bool bin;
+    bool fnbin;
+    void execute(const StaticInstBase *inst);
+
 #else
     Process *process;
 
@@ -176,7 +177,7 @@ class ExecContext
     unsigned storeCondFailures;
 
     // constructor: initialize context from given process structure
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
                 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
 #else
@@ -184,7 +185,7 @@ class ExecContext
     ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
                 int _asid);
 #endif
-    virtual ~ExecContext() {}
+    virtual ~ExecContext();
 
     virtual void takeOverFrom(ExecContext *oldContext);
 
@@ -193,11 +194,11 @@ class ExecContext
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     bool validInstAddr(Addr addr) { return true; }
     bool validDataAddr(Addr addr) { return true; }
-    int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
-    int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
+    int getInstAsid() { return regs.instAsid(); }
+    int getDataAsid() { return regs.dataAsid(); }
 
     Fault translateInstReq(MemReqPtr &req)
     {
@@ -253,20 +254,24 @@ class ExecContext
     template <class T>
     Fault read(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
         if (req->flags & LOCKED) {
             MiscRegFile *cregs = &req->xc->regs.miscRegs;
             cregs->lock_addr = req->paddr;
             cregs->lock_flag = true;
         }
 #endif
-        return mem->read(req, data);
+
+        Fault error;
+        error = mem->read(req, data);
+        data = gtoh(data);
+        return error;
     }
 
     template <class T>
     Fault write(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
 
         MiscRegFile *cregs;
 
@@ -309,7 +314,7 @@ class ExecContext
         }
 
 #endif
-        return mem->write(req, data);
+        return mem->write(req, (T)htog(data));
     }
 
     virtual bool misspeculating();
@@ -400,13 +405,13 @@ class ExecContext
         regs.miscRegs.fpcr = val;
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
     int readIntrFlag() { return regs.intrflag; }
     void setIntrFlag(int val) { regs.intrflag = val; }
     Fault hwrei();
-    bool inPalMode() { return PC_PAL(regs.pc); }
+    bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
     void ev5_trap(Fault fault);
     bool simPalCheck(int palFunc);
 #endif
@@ -419,7 +424,7 @@ class ExecContext
 
     void trap(Fault fault);
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     IntReg getSyscallArg(int i)
     {
         return regs.intRegFile[ArgumentReg0 + i];
@@ -431,20 +436,20 @@ class ExecContext
         regs.intRegFile[ArgumentReg0 + i] = val;
     }
 
-    void setSyscallReturn(int64_t return_value)
+    void setSyscallReturn(SyscallReturn return_value)
     {
         // check for error condition.  Alpha syscall convention is to
         // indicate success/failure in reg a3 (r19) and put the
         // return value itself in the standard return value reg (v0).
         const int RegA3 = 19;  // only place this is used
-        if (return_value >= 0) {
+        if (return_value.successful()) {
             // no error
             regs.intRegFile[RegA3] = 0;
-            regs.intRegFile[ReturnValueReg] = return_value;
+            regs.intRegFile[ReturnValueReg] = return_value.value();
         } else {
             // got an error, return details
             regs.intRegFile[RegA3] = (IntReg) -1;
-            regs.intRegFile[ReturnValueReg] = -return_value;
+            regs.intRegFile[ReturnValueReg] = -return_value.value();
         }
     }
 
@@ -463,4 +468,4 @@ ExecContext::misspeculating()
     return false;
 }
 
-#endif // __EXEC_CONTEXT_HH__
+#endif // __CPU_EXEC_CONTEXT_HH__