/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include <string>
#include <vector>
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
#include "sim/sim_object.hh"
: SimObject(name), cpu(c)
{}
+/* @todo
+ *Fix the cpu sim object parameter to be a system pointer
+ *instead, to avoid some extra dereferencing
+ */
+void
+IntrControl::post(int int_num, int index)
+{
+ std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
+ BaseCPU *temp = xcvec[0]->cpu;
+ temp->post_interrupt(int_num, index);
+}
+
+void
+IntrControl::post(int cpu_id, int int_num, int index)
+{
+ std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
+ BaseCPU *temp = xcvec[cpu_id]->cpu;
+ temp->post_interrupt(int_num, index);
+}
+
+void
+IntrControl::clear(int int_num, int index)
+{
+ std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
+ BaseCPU *temp = xcvec[0]->cpu;
+ temp->clear_interrupt(int_num, index);
+}
+
+void
+IntrControl::clear(int cpu_id, int int_num, int index)
+{
+ std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
+ BaseCPU *temp = xcvec[cpu_id]->cpu;
+ temp->clear_interrupt(int_num, index);
+}
+
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
SimObjectParam<BaseCPU *> cpu;
BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
- INIT_PARAM(cpu, "the processor")
+ INIT_PARAM(cpu, "the cpu")
END_INIT_SIM_OBJECT_PARAMS(IntrControl)