#else // !FULL_SYSTEM
#include "eio/eio.hh"
#include "mem/functional_mem/functional_memory.hh"
-#include "sim/prog.hh"
#endif // FULL_SYSTEM
using namespace std;
+SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
+ : Event(&mainEventQueue, 100), cpu(c)
+{
+}
+
+void
+SimpleCPU::TickEvent::process()
+{
+ cpu->tick();
+}
+
+const char *
+SimpleCPU::TickEvent::description()
+{
+ return "SimpleCPU tick event";
+}
+
+
SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
: Event(&mainEventQueue),
cpu(_cpu)
const char *
SimpleCPU::CacheCompletionEvent::description()
{
- return "cache completion event";
+ return "SimpleCPU cache completion event";
}
#ifdef FULL_SYSTEM
memReq->data = new uint8_t[64];
numInst = 0;
+ startNumInst = 0;
numLoad = 0;
- last_idle = 0;
+ startNumLoad = 0;
lastIcacheStall = 0;
lastDcacheStall = 0;
{
}
-
void
SimpleCPU::switchOut()
{
void
SimpleCPU::regStats()
{
+ using namespace Statistics;
+
BaseCPU::regStats();
numInsts
.desc("Number of memory references")
;
- idleCycles
- .name(name() + ".idle_cycles")
- .desc("Number of idle cycles")
- ;
-
idleFraction
.name(name() + ".idle_fraction")
.desc("Percentage of idle cycles")
.prereq(dcacheStallCycles)
;
- idleFraction = idleCycles / simTicks;
-
- numInsts = Statistics::scalar(numInst);
+ numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
simInsts += numInsts;
}
+void
+SimpleCPU::resetStats()
+{
+ startNumInst = numInst;
+}
+
void
SimpleCPU::serialize(ostream &os)
{
+ SERIALIZE_ENUM(_status);
+ SERIALIZE_SCALAR(inst);
+ nameOut(os, csprintf("%s.xc", name()));
xc->serialize(os);
+ nameOut(os, csprintf("%s.tickEvent", name()));
+ tickEvent.serialize(os);
+ nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
+ cacheCompletionEvent.serialize(os);
}
void
-SimpleCPU::unserialize(IniFile &db, const string &category)
+SimpleCPU::unserialize(Checkpoint *cp, const string §ion)
{
- string data;
-
- for (int i = 0; i < NumIntRegs; i++) {
- stringstream buf;
- ccprintf(buf, "R%02d", i);
- db.findDefault(category, buf.str(), data);
- to_number(data,xc->regs.intRegFile[i]);
- }
- for (int i = 0; i < NumFloatRegs; i++) {
- stringstream buf;
- ccprintf(buf, "F%02d", i);
- db.findDefault(category, buf.str(), data);
- to_number(data.c_str(), xc->regs.floatRegFile.q[i]);
- }
-
- // Read in Special registers
-
- // CPUTraitsType::unserializeSpecialRegs(db,category,node,xc->regs);
+ UNSERIALIZE_ENUM(_status);
+ UNSERIALIZE_SCALAR(inst);
+ xc->unserialize(cp, csprintf("%s.xc", section));
+ tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
+ cacheCompletionEvent
+ .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
}
void
xc->func_exe_insn++;
fault = si->execute(this, xc, traceData);
-
+#ifdef FS_MEASURE
+ if (!(xc->misspeculating()) && (xc->system->bin)) {
+ SWContext *ctx = xc->swCtx;
+ if (ctx && !ctx->callStack.empty()) {
+ if (si->isCall()) {
+ ctx->calls++;
+ }
+ if (si->isReturn()) {
+ if (ctx->calls == 0) {
+ fnCall *top = ctx->callStack.top();
+ DPRINTF(TCPIP, "Removing %s from callstack.\n", top->name);
+ delete top;
+ ctx->callStack.pop();
+ if (ctx->callStack.empty())
+ xc->system->nonPath->activate();
+ else
+ ctx->callStack.top()->myBin->activate();
+
+ xc->system->dumpState(xc);
+ } else {
+ ctx->calls--;
+ }
+ }
+ }
+ }
+#endif
if (si->isMemRef()) {
numMemRefs++;
}