undo simple CPU changes

[gem5.git] / cpu / simple_cpu / simple_cpu.cc

diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 18e6604835f6b31cbb0bbbaeea35225e1971910f..d48f936638eb3bc86972c8f36aab579816b7aedf 100644 (file)
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -123,11 +123,12 @@ SimpleCPU::SimpleCPU(const string &_name,
                      FunctionalMemory *mem,
                      MemInterface *icache_interface,
                      MemInterface *dcache_interface,
-                     bool _def_reg, Tick freq)
-    : BaseCPU(_name, /* number_of_threads */ 1,
+                     bool _def_reg, Tick freq,
+                     bool _function_trace, Tick _function_trace_start)
+    : BaseCPU(_name, /* number_of_threads */ 1, _def_reg,
               max_insts_any_thread, max_insts_all_threads,
               max_loads_any_thread, max_loads_all_threads,
-              _system, freq),
+              _system, freq, _function_trace, _function_trace_start),
 #else
 SimpleCPU::SimpleCPU(const string &_name, Process *_process,
                      Counter max_insts_any_thread,
@@ -136,13 +137,14 @@ SimpleCPU::SimpleCPU(const string &_name, Process *_process,
                      Counter max_loads_all_threads,
                      MemInterface *icache_interface,
                      MemInterface *dcache_interface,
-                     bool _def_reg)
-    : BaseCPU(_name, /* number_of_threads */ 1,
+                     bool _def_reg,
+                     bool _function_trace, Tick _function_trace_start)
+    : BaseCPU(_name, /* number_of_threads */ 1, _def_reg,
               max_insts_any_thread, max_insts_all_threads,
-              max_loads_any_thread, max_loads_all_threads),
+              max_loads_any_thread, max_loads_all_threads,
+              _function_trace, _function_trace_start),
 #endif
-      tickEvent(this), xc(NULL), defer_registration(_def_reg),
-      cacheCompletionEvent(this)
+      tickEvent(this), xc(NULL), cacheCompletionEvent(this)
 {
     _status = Idle;
 #ifdef FULL_SYSTEM
@@ -176,13 +178,6 @@ SimpleCPU::~SimpleCPU()
 {
 }
 
-void SimpleCPU::init()
-{
-    if (!defer_registration) {
-        this->registerExecContexts();
-    }
-}
-
 void
 SimpleCPU::switchOut()
 {
@@ -345,12 +340,13 @@ SimpleCPU::copySrcTranslate(Addr src)
     int offset = src & (blk_size - 1);
 
     // Make sure block doesn't span page
-    if (no_warn && (src & (~8191)) == ((src + blk_size) & (~8191))) {
-        warn("Copied block source spans pages.");
+    if (no_warn &&
+        (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
+        (src >> 40) != 0xfffffc) {
+        warn("Copied block source spans pages %x.", src);
         no_warn = false;
     }
 
-
     memReq->reset(src & ~(blk_size - 1), blk_size);
 
     // translate to physical address
@@ -380,9 +376,11 @@ SimpleCPU::copy(Addr dest)
     int offset = dest & (blk_size - 1);
 
     // Make sure block doesn't span page
-    if (no_warn && (dest & (~8191)) == ((dest + blk_size) & (~8191))) {
+    if (no_warn &&
+        (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
+        (dest >> 40) != 0xfffffc) {
         no_warn = false;
-        warn("Copied block destination spans pages. ");
+        warn("Copied block destination spans pages %x. ", dest);
     }
 
     memReq->reset(dest & ~(blk_size -1), blk_size);
@@ -398,6 +396,15 @@ SimpleCPU::copy(Addr dest)
         xc->mem->read(memReq, data);
         memReq->paddr = dest_addr;
         xc->mem->write(memReq, data);
+        if (dcacheInterface) {
+            memReq->cmd = Copy;
+            memReq->completionEvent = NULL;
+            memReq->paddr = xc->copySrcPhysAddr;
+            memReq->dest = dest_addr;
+            memReq->size = 64;
+            memReq->time = curTick;
+            dcacheInterface->access(memReq);
+        }
     }
     return fault;
 }
@@ -637,13 +644,11 @@ SimpleCPU::tick()
     Fault fault = No_Fault;
 
 #ifdef FULL_SYSTEM
-    if (AlphaISA::check_interrupts &&
-        xc->cpu->check_interrupts() &&
-        !PC_PAL(xc->regs.pc) &&
+    if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
         status() != IcacheMissComplete) {
         int ipl = 0;
         int summary = 0;
-        AlphaISA::check_interrupts = 0;
+        checkInterrupts = false;
         IntReg *ipr = xc->regs.ipr;
 
         if (xc->regs.ipr[TheISA::IPR_SIRR]) {
@@ -776,6 +781,8 @@ SimpleCPU::tick()
         if (traceData)
             traceData->finalize();
 
+        traceFunctions(xc->regs.pc);
+
     }  // if (fault == No_Fault)
 
     if (fault != No_Fault) {
@@ -834,6 +841,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
 
     Param<bool> defer_registration;
     Param<int> multiplier;
+    Param<bool> function_trace;
+    Param<Tick> function_trace_start;
 
 END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
 
@@ -867,7 +876,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
     INIT_PARAM_DFLT(defer_registration, "defer registration with system "
                     "(for sampling)", false),
 
-    INIT_PARAM_DFLT(multiplier, "clock multiplier", 1)
+    INIT_PARAM_DFLT(multiplier, "clock multiplier", 1),
+    INIT_PARAM_DFLT(function_trace, "Enable function trace", false),
+    INIT_PARAM_DFLT(function_trace_start, "Cycle to start function trace", 0)
 
 END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
 
@@ -886,7 +897,8 @@ CREATE_SIM_OBJECT(SimpleCPU)
                         (icache) ? icache->getInterface() : NULL,
                         (dcache) ? dcache->getInterface() : NULL,
                         defer_registration,
-                        ticksPerSecond * mult);
+                        ticksPerSecond * mult,
+                        function_trace, function_trace_start);
 #else
 
     cpu = new SimpleCPU(getInstanceName(), workload,
@@ -894,7 +906,8 @@ CREATE_SIM_OBJECT(SimpleCPU)
                         max_loads_any_thread, max_loads_all_threads,
                         (icache) ? icache->getInterface() : NULL,
                         (dcache) ? dcache->getInterface() : NULL,
-                        defer_registration);
+                        defer_registration,
+                        function_trace, function_trace_start);
 
 #endif // FULL_SYSTEM