Merged in new FastCPU stuff with existing code.

[gem5.git] / cpu / simple_cpu / simple_cpu.hh

diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 2b881509c892eb4309c8e14f7f2c80414e9a5a2e..1c6b18d039ae0acbcf77d9e34a89d89e023128ed 100644 (file)
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -34,18 +34,24 @@
 #include "base/loader/symtab.hh"
 #include "cpu/pc_event.hh"
 #include "base/statistics.hh"
-
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
 
 // forward declarations
 #ifdef FULL_SYSTEM
 class Processor;
 class Kernel;
-class AlphaItb;
-class AlphaDtb;
+class AlphaITB;
+class AlphaDTB;
 class PhysicalMemory;
 
 class RemoteGDB;
 class GDBListener;
+
+#else
+
+class Process;
+
 #endif // FULL_SYSTEM
 
 class MemInterface;
@@ -131,7 +137,7 @@ class SimpleCPU : public BaseCPU
               System *_system,
               Counter max_insts_any_thread, Counter max_insts_all_threads,
               Counter max_loads_any_thread, Counter max_loads_all_threads,
-              AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
+              AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem,
               MemInterface *icache_interface, MemInterface *dcache_interface,
               bool _def_reg, Tick freq);
 
@@ -204,25 +210,30 @@ class SimpleCPU : public BaseCPU
     // number of simulated instructions
     Counter numInst;
     Counter startNumInst;
-    Statistics::Formula numInsts;
+    Stats::Scalar<> numInsts;
+
+    virtual Counter totalInstructions() const
+    {
+        return numInst - startNumInst;
+    }
 
     // number of simulated memory references
-    Statistics::Scalar<> numMemRefs;
+    Stats::Scalar<> numMemRefs;
 
     // number of simulated loads
     Counter numLoad;
     Counter startNumLoad;
 
     // number of idle cycles
-    Statistics::Average<> notIdleFraction;
-    Statistics::Formula idleFraction;
+    Stats::Average<> notIdleFraction;
+    Stats::Formula idleFraction;
 
     // number of cycles stalled for I-cache misses
-    Statistics::Scalar<> icacheStallCycles;
+    Stats::Scalar<> icacheStallCycles;
     Counter lastIcacheStall;
 
     // number of cycles stalled for D-cache misses
-    Statistics::Scalar<> dcacheStallCycles;
+    Stats::Scalar<> dcacheStallCycles;
     Counter lastDcacheStall;
 
     void processCacheCompletion();
@@ -246,6 +257,92 @@ class SimpleCPU : public BaseCPU
     {
         // need to do this...
     }
+
+    Fault copySrcTranslate(Addr src);
+
+    Fault copy(Addr dest);
+
+    // The register accessor methods provide the index of the
+    // instruction's operand (e.g., 0 or 1), not the architectural
+    // register index, to simplify the implementation of register
+    // renaming.  We find the architectural register index by indexing
+    // into the instruction's own operand index table.  Note that a
+    // raw pointer to the StaticInst is provided instead of a
+    // ref-counted StaticInstPtr to redice overhead.  This is fine as
+    // long as these methods don't copy the pointer into any long-term
+    // storage (which is pretty hard to imagine they would have reason
+    // to do).
+
+    uint64_t readIntReg(StaticInst<TheISA> *si, int idx)
+    {
+        return xc->readIntReg(si->srcRegIdx(idx));
+    }
+
+    float readFloatRegSingle(StaticInst<TheISA> *si, int idx)
+    {
+        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+        return xc->readFloatRegSingle(reg_idx);
+    }
+
+    double readFloatRegDouble(StaticInst<TheISA> *si, int idx)
+    {
+        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+        return xc->readFloatRegDouble(reg_idx);
+    }
+
+    uint64_t readFloatRegInt(StaticInst<TheISA> *si, int idx)
+    {
+        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+        return xc->readFloatRegInt(reg_idx);
+    }
+
+    void setIntReg(StaticInst<TheISA> *si, int idx, uint64_t val)
+    {
+        xc->setIntReg(si->destRegIdx(idx), val);
+    }
+
+    void setFloatRegSingle(StaticInst<TheISA> *si, int idx, float val)
+    {
+        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+        xc->setFloatRegSingle(reg_idx, val);
+    }
+
+    void setFloatRegDouble(StaticInst<TheISA> *si, int idx, double val)
+    {
+        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+        xc->setFloatRegDouble(reg_idx, val);
+    }
+
+    void setFloatRegInt(StaticInst<TheISA> *si, int idx, uint64_t val)
+    {
+        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+        xc->setFloatRegInt(reg_idx, val);
+    }
+
+    uint64_t readPC() { return xc->readPC(); }
+    void setNextPC(uint64_t val) { xc->setNextPC(val); }
+
+    uint64_t readUniq() { return xc->readUniq(); }
+    void setUniq(uint64_t val) { xc->setUniq(val); }
+
+    uint64_t readFpcr() { return xc->readFpcr(); }
+    void setFpcr(uint64_t val) { xc->setFpcr(val); }
+
+#ifdef FULL_SYSTEM
+    uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
+    Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
+    Fault hwrei() { return xc->hwrei(); }
+    int readIntrFlag() { return xc->readIntrFlag(); }
+    void setIntrFlag(int val) { xc->setIntrFlag(val); }
+    bool inPalMode() { return xc->inPalMode(); }
+    void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
+    bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
+#else
+    void syscall() { xc->syscall(); }
+#endif
+
+    bool misspeculating() { return xc->misspeculating(); }
+    ExecContext *xcBase() { return xc; }
 };
 
 #endif // __SIMPLE_CPU_HH__