/*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include <bitset>
#include <string>
-#include "sim/host.hh"
#include "base/hashmap.hh"
#include "base/refcnt.hh"
-
-#include "cpu/full_cpu/op_class.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "sim/host.hh"
#include "targetarch/isa_traits.hh"
// forward declarations
struct AlphaSimpleImpl;
-struct OoOImpl;
class ExecContext;
class DynInst;
template <class Impl>
class AlphaDynInst;
-template <class Impl>
-class OoODynInst;
-
class FastCPU;
class SimpleCPU;
class InorderCPU;
* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
* just the EA computation.
*/
- virtual
+ virtual const
StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
/**
* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
* just the memory access (not the EA computation).
*/
- virtual
+ virtual const
StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
/// The binary machine instruction.
* String representation of disassembly (lazily evaluated via
* disassemble()).
*/
- std::string *cachedDisassembly;
+ mutable std::string *cachedDisassembly;
/**
* Internal function to generate disassembly string.
*/
- virtual std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) = 0;
+ virtual std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
/// Constructor.
StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
* Return true if the instruction is a control transfer, and if so,
* return the target address as well.
*/
- bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
+ bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
/**
* Return string representation of disassembled instruction.
* should not be cached, this function should be overridden directly.
*/
virtual const std::string &disassemble(Addr pc,
- const SymbolTable *symtab = 0)
+ const SymbolTable *symtab = 0) const
{
if (!cachedDisassembly)
cachedDisassembly =