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[gem5.git] / cpu / static_inst.hh

diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 25c98b12ad876fe7f5831c700f7bef5fc75241ab..85cfb5ae786c8be1b9b9924ef3515526a46bc984 100644 (file)
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -32,25 +32,20 @@
 #include <bitset>
 #include <string>
 
-#include "sim/host.hh"
 #include "base/hashmap.hh"
 #include "base/refcnt.hh"
-
-#include "cpu/full_cpu/op_class.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "sim/host.hh"
 #include "targetarch/isa_traits.hh"
 
 // forward declarations
 struct AlphaSimpleImpl;
-struct OoOImpl;
 class ExecContext;
 class DynInst;
 
 template <class Impl>
 class AlphaDynInst;
 
-template <class Impl>
-class OoODynInst;
-
 class FastCPU;
 class SimpleCPU;
 class InorderCPU;
@@ -260,7 +255,7 @@ class StaticInst : public StaticInstBase
      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
      * just the EA computation.
      */
-    virtual
+    virtual const
     StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
 
     /**
@@ -269,7 +264,7 @@ class StaticInst : public StaticInstBase
      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
      * just the memory access (not the EA computation).
      */
-    virtual
+    virtual const
     StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
 
     /// The binary machine instruction.
@@ -294,13 +289,13 @@ class StaticInst : public StaticInstBase
      * String representation of disassembly (lazily evaluated via
      * disassemble()).
      */
-    std::string *cachedDisassembly;
+    mutable std::string *cachedDisassembly;
 
     /**
      * Internal function to generate disassembly string.
      */
-    virtual std::string generateDisassembly(Addr pc,
-                                            const SymbolTable *symtab) = 0;
+    virtual std::string
+    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 
     /// Constructor.
     StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
@@ -347,7 +342,7 @@ class StaticInst : public StaticInstBase
      * Return true if the instruction is a control transfer, and if so,
      * return the target address as well.
      */
-    bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
+    bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
 
     /**
      * Return string representation of disassembled instruction.
@@ -357,7 +352,7 @@ class StaticInst : public StaticInstBase
      * should not be cached, this function should be overridden directly.
      */
     virtual const std::string &disassemble(Addr pc,
-                                           const SymbolTable *symtab = 0)
+                                           const SymbolTable *symtab = 0) const
     {
         if (!cachedDisassembly)
             cachedDisassembly =