/*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include <bitset>
#include <string>
-#include "sim/host.hh"
#include "base/hashmap.hh"
#include "base/refcnt.hh"
-
-#include "cpu/full_cpu/op_class.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "sim/host.hh"
#include "targetarch/isa_traits.hh"
// forward declarations
struct AlphaSimpleImpl;
-struct OoOImpl;
class ExecContext;
class DynInst;
template <class Impl>
class AlphaDynInst;
-template <class Impl>
-class OoODynInst;
-
class FastCPU;
class SimpleCPU;
class InorderCPU;
* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
* just the EA computation.
*/
- virtual
+ virtual const
StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
/**
* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
* just the memory access (not the EA computation).
*/
- virtual
+ virtual const
StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
/// The binary machine instruction.