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[gem5.git] / cpu / static_inst.hh

diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 57208f8e6f1c0d0b99b93a2b6570ab70ed92c862..85cfb5ae786c8be1b9b9924ef3515526a46bc984 100644 (file)
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -26,25 +26,29 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __STATIC_INST_HH__
-#define __STATIC_INST_HH__
+#ifndef __CPU_STATIC_INST_HH__
+#define __CPU_STATIC_INST_HH__
 
 #include <bitset>
 #include <string>
 
-#include "sim/host.hh"
 #include "base/hashmap.hh"
 #include "base/refcnt.hh"
-
-#include "cpu/full_cpu/op_class.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "sim/host.hh"
 #include "targetarch/isa_traits.hh"
 
 // forward declarations
+struct AlphaSimpleImpl;
 class ExecContext;
 class DynInst;
-typedef DynInst FullCPUExecContext;
+
+template <class Impl>
+class AlphaDynInst;
+
+class FastCPU;
 class SimpleCPU;
-typedef SimpleCPU SimpleCPUExecContext;
+class InorderCPU;
 class SymbolTable;
 
 namespace Trace {
@@ -73,8 +77,7 @@ class StaticInstBase : public RefCounted
     /// unconditional branches, memory barriers) or both (e.g., an
     /// FP/int conversion).
     /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
-    /// will be set.  Prefetches are marked as IsLoad, even if they
-    /// prefetch exclusive copies.
+    /// will be set.
     /// - If IsControl is set, then exactly one of IsDirectControl or
     /// IsIndirect Control will be set, and exactly one of
     /// IsCondControl or IsUncondControl will be set.
@@ -108,11 +111,13 @@ class StaticInstBase : public RefCounted
 
         IsThreadSync,  ///< Thread synchronization operation.
 
-        IsSerializing, ///< Serializes pipeline: won't until all
+        IsSerializing, ///< Serializes pipeline: won't execute until all
                         /// older instructions have committed.
         IsMemBarrier,  ///< Is a memory barrier
         IsWriteBarrier,        ///< Is a write barrier
 
+        IsNonSpeculative, ///< Should not be executed speculatively
+
         NumFlags
     };
 
@@ -194,6 +199,7 @@ class StaticInstBase : public RefCounted
     bool isSerializing()  const { return flags[IsSerializing]; }
     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
+    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
     //@}
 
     /// Operation class.  Used to select appropriate function unit in issue.
@@ -249,7 +255,8 @@ class StaticInst : public StaticInstBase
      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
      * just the EA computation.
      */
-    virtual StaticInstPtr<ISA> eaCompInst() { return nullStaticInstPtr; }
+    virtual const
+    StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
 
     /**
      * Memory references only: returns "fake" instruction representing
@@ -257,7 +264,8 @@ class StaticInst : public StaticInstBase
      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
      * just the memory access (not the EA computation).
      */
-    virtual StaticInstPtr<ISA> memAccInst() { return nullStaticInstPtr; }
+    virtual const
+    StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
 
     /// The binary machine instruction.
     const MachInst machInst;
@@ -281,13 +289,13 @@ class StaticInst : public StaticInstBase
      * String representation of disassembly (lazily evaluated via
      * disassemble()).
      */
-    std::string *cachedDisassembly;
+    mutable std::string *cachedDisassembly;
 
     /**
      * Internal function to generate disassembly string.
      */
-    virtual std::string generateDisassembly(Addr pc,
-                                            const SymbolTable *symtab) = 0;
+    virtual std::string
+    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 
     /// Constructor.
     StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
@@ -304,17 +312,7 @@ class StaticInst : public StaticInstBase
             delete cachedDisassembly;
     }
 
-    /**
-     * Execute this instruction under SimpleCPU model.
-     */
-    virtual Fault execute(SimpleCPUExecContext *xc,
-                          Trace::InstRecord *traceData) = 0;
-
-    /**
-     * Execute this instruction under detailed FullCPU model.
-     */
-    virtual Fault execute(FullCPUExecContext *xc,
-                          Trace::InstRecord *traceData) = 0;
+#include "static_inst_impl.hh"
 
     /**
      * Return the target address for a PC-relative branch.
@@ -344,7 +342,7 @@ class StaticInst : public StaticInstBase
      * Return true if the instruction is a control transfer, and if so,
      * return the target address as well.
      */
-    bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
+    bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
 
     /**
      * Return string representation of disassembled instruction.
@@ -354,7 +352,7 @@ class StaticInst : public StaticInstBase
      * should not be cached, this function should be overridden directly.
      */
     virtual const std::string &disassemble(Addr pc,
-                                           const SymbolTable *symtab = 0)
+                                           const SymbolTable *symtab = 0) const
     {
         if (!cachedDisassembly)
             cachedDisassembly =
@@ -443,8 +441,8 @@ class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
     /// Convert to pointer to StaticInstBase class.
     operator const StaticInstBasePtr()
     {
-        return get();
+        return this->get();
     }
 };
 
-#endif // __STATIC_INST_HH__
+#endif // __CPU_STATIC_INST_HH__