/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __STATIC_INST_HH__
-#define __STATIC_INST_HH__
+#ifndef __CPU_STATIC_INST_HH__
+#define __CPU_STATIC_INST_HH__
#include <bitset>
#include <string>
-#include "sim/host.hh"
#include "base/hashmap.hh"
#include "base/refcnt.hh"
-
-#include "cpu/full_cpu/op_class.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "sim/host.hh"
#include "targetarch/isa_traits.hh"
// forward declarations
+struct AlphaSimpleImpl;
class ExecContext;
-class SpecExecContext;
-class SimpleCPU;
-class FullCPU;
class DynInst;
+
+template <class Impl>
+class AlphaDynInst;
+
+class FastCPU;
+class SimpleCPU;
+class InorderCPU;
class SymbolTable;
namespace Trace {
/// unconditional branches, memory barriers) or both (e.g., an
/// FP/int conversion).
/// - If IsMemRef is set, then exactly one of IsLoad or IsStore
- /// will be set. Prefetches are marked as IsLoad, even if they
- /// prefetch exclusive copies.
+ /// will be set.
/// - If IsControl is set, then exactly one of IsDirectControl or
/// IsIndirect Control will be set, and exactly one of
/// IsCondControl or IsUncondControl will be set.
+ /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
+ /// implemented as flags since in the current model there's no
+ /// other way for instructions to inject behavior into the
+ /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
+ /// model we should be able to get rid of these flags and
+ /// implement this behavior via the execute() methods.
///
enum Flags {
IsNop, ///< Is a no-op (no effect at all).
IsStore, ///< Writes to memory.
IsInstPrefetch, ///< Instruction-cache prefetch.
IsDataPrefetch, ///< Data-cache prefetch.
+ IsCopy, ///< Fast Cache block copy
IsControl, ///< Control transfer instruction.
IsDirectControl, ///< PC relative control transfer.
IsCall, ///< Subroutine call.
IsReturn, ///< Subroutine return.
- IsThreadSync, ///< Thread synchronization operation.
+ IsThreadSync, ///< Thread synchronization operation.
+
+ IsSerializing, ///< Serializes pipeline: won't execute until all
+ /// older instructions have committed.
+ IsMemBarrier, ///< Is a memory barrier
+ IsWriteBarrier, ///< Is a write barrier
+
+ IsNonSpeculative, ///< Should not be executed speculatively
NumFlags
};
bool isStore() const { return flags[IsStore]; }
bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
+ bool isCopy() const { return flags[IsCopy];}
bool isInteger() const { return flags[IsInteger]; }
bool isFloating() const { return flags[IsFloating]; }
bool isUncondCtrl() const { return flags[IsUncondControl]; }
bool isThreadSync() const { return flags[IsThreadSync]; }
+ bool isSerializing() const { return flags[IsSerializing]; }
+ bool isMemBarrier() const { return flags[IsMemBarrier]; }
+ bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
+ bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
//@}
/// Operation class. Used to select appropriate function unit in issue.
/// Return logical index (architectural reg num) of i'th destination reg.
/// Only the entries from 0 through numDestRegs()-1 are valid.
- RegIndex destRegIdx(int i) { return _destRegIdx[i]; }
+ RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
/// Return logical index (architectural reg num) of i'th source reg.
/// Only the entries from 0 through numSrcRegs()-1 are valid.
- RegIndex srcRegIdx(int i) { return _srcRegIdx[i]; }
+ RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
/// Pointer to a statically allocated "null" instruction object.
/// Used to give eaCompInst() and memAccInst() something to return
* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
* just the EA computation.
*/
- virtual StaticInstPtr<ISA> eaCompInst() { return nullStaticInstPtr; }
+ virtual const
+ StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
/**
* Memory references only: returns "fake" instruction representing
* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
* just the memory access (not the EA computation).
*/
- virtual StaticInstPtr<ISA> memAccInst() { return nullStaticInstPtr; }
+ virtual const
+ StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
/// The binary machine instruction.
const MachInst machInst;
* String representation of disassembly (lazily evaluated via
* disassemble()).
*/
- std::string *cachedDisassembly;
+ mutable std::string *cachedDisassembly;
/**
* Internal function to generate disassembly string.
*/
- virtual std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) = 0;
+ virtual std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
/// Constructor.
StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
delete cachedDisassembly;
}
- /**
- * Execute this instruction under SimpleCPU model.
- */
- virtual Fault execute(SimpleCPU *cpu, ExecContext *xc,
- Trace::InstRecord *traceData) = 0;
-
- /**
- * Execute this instruction under detailed FullCPU model.
- */
- virtual Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
- Trace::InstRecord *traceData) = 0;
+#include "static_inst_impl.hh"
/**
* Return the target address for a PC-relative branch.
* Invalid if not a PC-relative branch (i.e. isDirectCtrl()
* should be true).
*/
- virtual Addr branchTarget(Addr branchPC)
+ virtual Addr branchTarget(Addr branchPC) const
{
panic("StaticInst::branchTarget() called on instruction "
"that is not a PC-relative branch.");
}
/**
- * Return the target address for an indirect branch (jump).
- * The register value is read from the supplied execution context.
- * Invalid if not an indirect branch (i.e. isIndirectCtrl()
- * should be true).
+ * Return the target address for an indirect branch (jump). The
+ * register value is read from the supplied execution context, so
+ * the result is valid only if the execution context is about to
+ * execute the branch in question. Invalid if not an indirect
+ * branch (i.e. isIndirectCtrl() should be true).
*/
- virtual Addr branchTarget(ExecContext *xc)
+ virtual Addr branchTarget(ExecContext *xc) const
{
panic("StaticInst::branchTarget() called on instruction "
"that is not an indirect branch.");
* Return true if the instruction is a control transfer, and if so,
* return the target address as well.
*/
- bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
+ bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
/**
* Return string representation of disassembled instruction.
* should not be cached, this function should be overridden directly.
*/
virtual const std::string &disassemble(Addr pc,
- const SymbolTable *symtab = 0)
+ const SymbolTable *symtab = 0) const
{
if (!cachedDisassembly)
cachedDisassembly =
/// Convert to pointer to StaticInstBase class.
operator const StaticInstBasePtr()
{
- return get();
+ return this->get();
}
};
-#endif // __STATIC_INST_HH__
+#endif // __CPU_STATIC_INST_HH__
projects / gem5.git / blobdiff