/*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __STATIC_INST_HH__
-#define __STATIC_INST_HH__
+#ifndef __CPU_STATIC_INST_HH__
+#define __CPU_STATIC_INST_HH__
#include <bitset>
#include <string>
-#include "sim/host.hh"
#include "base/hashmap.hh"
#include "base/refcnt.hh"
-
-#include "cpu/full_cpu/op_class.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "sim/host.hh"
#include "targetarch/isa_traits.hh"
// forward declarations
+struct AlphaSimpleImpl;
class ExecContext;
class DynInst;
+
+template <class Impl>
+class AlphaDynInst;
+
class FastCPU;
class SimpleCPU;
class InorderCPU;
delete cachedDisassembly;
}
- /**
- * Execute this instruction under SimpleCPU model.
- */
- virtual Fault execute(SimpleCPU *xc,
- Trace::InstRecord *traceData) const = 0;
-
- /**
- * Execute this instruction under InorderCPU model.
- */
- virtual Fault execute(InorderCPU *xc,
- Trace::InstRecord *traceData) const = 0;
-
-
- /**
- * Execute this instruction under FastCPU model.
- */
- virtual Fault execute(FastCPU *xc,
- Trace::InstRecord *traceData) const = 0;
-
- /**
- * Execute this instruction under detailed FullCPU model.
- */
- virtual Fault execute(DynInst *xc,
- Trace::InstRecord *traceData) const = 0;
+#include "static_inst_impl.hh"
/**
* Return the target address for a PC-relative branch.
}
};
-#endif // __STATIC_INST_HH__
+#endif // __CPU_STATIC_INST_HH__