Merge ktlim@zizzer.eecs.umich.edu:/bk/m5

[gem5.git] / cpu / trace / opt_cpu.cc

diff --git a/cpu/trace/opt_cpu.cc b/cpu/trace/opt_cpu.cc
index 22d12f0792de83d6ff963dcdbeda4f16a4773afe..15b53d46eb70e908703b8ffa23e51371918af46f 100644 (file)
--- a/cpu/trace/opt_cpu.cc
+++ b/cpu/trace/opt_cpu.cc
@@ -48,11 +48,17 @@ OptCPU::OptCPU(const string &name,
                int block_size,
                int cache_size,
                int _assoc)
-    : BaseCPU(name,1), tickEvent(this), trace(_trace),
+    : SimObject(name), tickEvent(this), trace(_trace),
       numBlks(cache_size/block_size), assoc(_assoc), numSets(numBlks/assoc),
       setMask(numSets - 1)
 {
-    int log_block_size = (int)(log((double) block_size)/log(2.0));
+    int log_block_size = 0;
+    int tmp_block_size = block_size;
+    while (tmp_block_size > 1) {
+        ++log_block_size;
+        tmp_block_size = tmp_block_size >> 1;
+    }
+    assert(1<<log_block_size == block_size);
     MemReqPtr req;
     trace->getNextReq(req);
     refInfo.resize(numSets);
@@ -124,7 +130,7 @@ OptCPU::processSet(int set)
     for (int start = assoc/2; start >= 0; --start) {
         heapify(set,start);
     }
-    verifyHeap(set,0);
+    //verifyHeap(set,0);
 
     for (; i < refInfo[set].size(); ++i) {
         RefIndex cache_index = lookupValue(refInfo[set][i].addr);
@@ -134,8 +140,11 @@ OptCPU::processSet(int set)
             // replace from cacheHeap[0]
             // mark replaced block as absent
             setValue(refInfo[set][cacheHeap[0]].addr, -1);
+            setValue(refInfo[set][i].addr, 0);
             cacheHeap[0] = i;
             heapify(set, 0);
+            // Make sure its in the cache
+            assert(lookupValue(refInfo[set][i].addr) != -1);
         } else {
             // hit
             hits++;
@@ -143,9 +152,11 @@ OptCPU::processSet(int set)
                    refInfo[set][i].addr);
             assert(refInfo[set][cacheHeap[cache_index]].nextRefTime == i);
             assert(heapLeft(cache_index) >= assoc);
+
+            cacheHeap[cache_index] = i;
+            processRankIncrease(set, cache_index);
+            assert(lookupValue(refInfo[set][i].addr) != -1);
         }
-        cacheHeap[cache_index] = i;
-        processRankIncrease(set, cache_index);
     }
 }
 void
@@ -161,8 +172,9 @@ OptCPU::tick()
         references += refInfo[set].size();
     }
     // exit;
-    fprintf(stderr, "OPT Misses: %d\nOPT Hits: %d\nOPT Accesses: %d\n",
-            misses, hits, references);
+    fprintf(stderr,"sys.cpu.misses %d #opt cache misses\n",misses);
+    fprintf(stderr,"sys.cpu.hits %d #opt cache hits\n", hits);
+    fprintf(stderr,"sys.cpu.accesses %d #opt cache acceses\n", references);
     new SimExitEvent("Finshed Memory Trace");
 }