Merge ktlim@zizzer.eecs.umich.edu:/bk/m5

[gem5.git] / cpu / trace / opt_cpu.hh

diff --git a/cpu/trace/opt_cpu.hh b/cpu/trace/opt_cpu.hh
index 847147b3c542be97cdb94adb7a390a3769f805c3..7f6aa3e184eaa80021e6e45844bbd26e714a0745 100644 (file)
--- a/cpu/trace/opt_cpu.hh
+++ b/cpu/trace/opt_cpu.hh
@@ -32,14 +32,14 @@
  * trace to access a fully associative cache with optimal replacement.
  */
 
-#ifndef __OPT_CPU_HH__
-#define __OPT_CPU_HH__
+#ifndef __CPU_TRACE_OPT_CPU_HH__
+#define __CPU_TRACE_OPT_CPU_HH__
 
 #include <vector>
 
-#include "cpu/base_cpu.hh"
 #include "mem/mem_req.hh" // for MemReqPtr
 #include "sim/eventq.hh" // for Event
+#include "sim/sim_object.hh"
 
 // Forward Declaration
 class MemTraceReader;
@@ -47,8 +47,9 @@ class MemTraceReader;
 /**
  * A CPU object to simulate a fully-associative cache with optimal replacement.
  */
-class OptCPU : public BaseCPU
+class OptCPU : public SimObject
 {
+  private:
     typedef int RefIndex;
 
     typedef std::vector<RefIndex> L3Table;
@@ -219,4 +220,4 @@ class OptCPU : public BaseCPU
     void tick();
 };
 
-#endif
+#endif // __CPU_TRACE_OPT_CPU_HH__