self.meie = Signal(name="mie_meie")
self.mtie = Signal(name="mie_mtie")
self.msie = Signal(name="mie_msie")
+ self.seie = Signal(name="mie_seie")
self.ueie = Signal(name="mie_ueie")
self.stie = Signal(name="mie_stie")
self.utie = Signal(name="mie_utie")
self.sync += self.mtie.eq(0)
self.sync += self.msie.eq(0)
+ def make(self):
+ return Cat( self.usie, self.ssie, 0, self.msie,
+ self.utie, self.stie, 0, self.mtie,
+ self.ueie, self.seie, 0, self.meie, )
+
+
class MIP:
def __init__(self, comb, sync):
self.comb = comb
self.usip = Signal(name="mip_usip")
for n in dir(self):
- if n in ['comb', 'sync'] or n.startswith("_"):
+ if n in ['make', 'comb', 'sync'] or n.startswith("_"):
continue
self.comb += getattr(self, n).eq(0x0)
+ def make(self):
+ return Cat( self.usip, self.ssip, 0, self.msip,
+ self.utip, self.stip, 0, self.mtip,
+ self.ueip, self.seip, 0, self.meip, )
+
class M:
def __init__(self, comb, sync):
return Case(self.output_state, c)
+class CSR:
+ def __init__(self, comb, sync, dc, register_rs1):
+ self.comb = comb
+ self.sync = sync
+ self.number = Signal(12, name="csr_number")
+ self.input_value = Signal(32, name="csr_input_value")
+ self.reads = Signal(name="csr_reads")
+ self.writes = Signal(name="csr_writes")
+ self.op_is_valid = Signal(name="csr_op_is_valid")
+
+ self.comb += self.number.eq(dc.immediate)
+ self.comb += self.input_value.eq(Mux(dc.funct3[2],
+ dc.rs1,
+ register_rs1))
+ self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0))
+ self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
+
+ self.comb += self.get_csr_op_is_valid()
+
+ def get_csr_op_is_valid(self):
+ """ determines if a CSR is valid
+ """
+ c = {}
+ # invalid csrs
+ for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
+ csr_uie, csr_utvec, csr_uscratch, csr_uepc,
+ csr_ucause, csr_utval, csr_uip, csr_sstatus,
+ csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
+ csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
+ csr_stval, csr_sip, csr_satp, csr_medeleg,
+ csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
+ c[f] = self.op_is_valid.eq(0)
+
+ # not-writeable -> ok
+ for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
+ csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
+ csr_mimpid, csr_mhartid]:
+ c[f] = self.op_is_valid.eq(~self.writes)
+
+ # valid csrs
+ for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
+ csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
+ c[f] = self.op_is_valid.eq(1)
+
+ # not implemented / default
+ for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
+ csr_mcycleh, csr_minstreth, "default"]:
+ c[f] = self.op_is_valid.eq(0)
+
+ return Case(self.number, c)
+
+ def evaluate_csr_funct3_op(self, funct3, previous, written):
+ c = { "default": written.eq(Constant(0, 32))}
+ for f in [F3.csrrw, F3.csrrwi]:
+ c[f] = written.eq(self.input_value)
+ for f in [F3.csrrs, F3.csrrsi]:
+ c[f] = written.eq(self.input_value | previous)
+ for f in [F3.csrrc, F3.csrrci]:
+ c[f] = written.eq(~self.input_value & previous)
+ return Case(funct3, c)
+
+
+class MInfo:
+ def __init__(self, comb):
+ self.comb = comb
+ # TODO
+ self.cycle_counter = Signal(64); # TODO: implement cycle_counter
+ self.time_counter = Signal(64); # TODO: implement time_counter
+ self.instret_counter = Signal(64); # TODO: implement instret_counter
+
+ self.mvendorid = Signal(32)
+ self.marchid = Signal(32)
+ self.mimpid = Signal(32)
+ self.mhartid = Signal(32)
+ self.comb += self.mvendorid.eq(Constant(0, 32))
+ self.comb += self.marchid.eq(Constant(0, 32))
+ self.comb += self.mimpid.eq(Constant(0, 32))
+ self.comb += self.mhartid.eq(Constant(0, 32))
+
class CPU(Module):
"""
self.registers[register_number].eq(value)
)
- def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
- c = { "default": Constant(0, 32)}
- for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
- for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
- for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
- return Case(funct3, c)
-
def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
s = [ms.mpie.eq(ms.mie),
ms.mie.eq(0),
s.append(i)
return s
- def get_csr_op_is_valid(self, csr_op_is_valid, csr_number,
- csr_reads, csr_writes):
- """ determines if a CSR is valid
- """
+ def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
+ ft, dc,
+ load_store_misaligned,
+ loaded_value, alu_result,
+ lui_auipc_result):
c = {}
- # invalid csrs
- for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
- csr_uie, csr_utvec, csr_uscratch, csr_uepc,
- csr_ucause, csr_utval, csr_uip, csr_sstatus,
- csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
- csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
- csr_stval, csr_sip, csr_satp, csr_medeleg,
- csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
- c[f] = csr_op_is_valid.eq(0)
+ c[FOS.empty] = []
+ c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
+ load_store_misaligned)
+ c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
+ mstatus, mie, ft, dc,
+ load_store_misaligned,
+ loaded_value,
+ alu_result,
+ lui_auipc_result)
+ return Case(ft.output_state, c)
+
+ def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
+ ft, dc,
+ load_store_misaligned,
+ loaded_value, alu_result,
+ lui_auipc_result):
+ # fetch action ack trap
+ i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
+ self.handle_trap(m, mstatus, ft, dc,
+ load_store_misaligned)
+ )
- # not-writeable -> ok
- for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
- csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
- csr_mimpid, csr_mhartid]:
- c[f] = csr_op_is_valid.eq(~csr_writes)
+ # load
+ i = i.Elif((dc.act & DA.load) != 0,
+ If(~mi.rw_wait,
+ self.write_register(dc.rd, loaded_value)
+ )
+ )
- # valid csrs
- for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
- csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
- c[f] = csr_op_is_valid.eq(1)
+ # op or op_immediate
+ i = i.Elif((dc.act & DA.op_op_imm) != 0,
+ self.write_register(dc.rd, alu_result)
+ )
- # not implemented / default
- for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
- csr_mcycleh, csr_minstreth, "default"]:
- c[f] = csr_op_is_valid.eq(0)
+ # lui or auipc
+ i = i.Elif((dc.act & DA.lui_auipc) != 0,
+ self.write_register(dc.rd, lui_auipc_result)
+ )
+
+ # jal/jalr
+ i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
+ self.write_register(dc.rd, ft.output_pc + 4)
+ )
+
+ i = i.Elif((dc.act & DA.csr) != 0,
+ self.handle_csr(mtvec, mip, minfo, misa, mstatus, mie, m,
+ dc, csr)
+ )
+
+ # fence, store, branch
+ i = i.Elif((dc.act & (DA.fence | DA.fence_i |
+ DA.store | DA.branch)) != 0,
+ # do nothing
+ )
- return Case(csr_number, c)
+ return i
+ def handle_csr(self, mtvec, mip, minfo, misa, mstatus, mie, m, dc, csr):
+ csr_output_value = Signal(32)
+ csr_written_value = Signal(32)
+ c = {}
+
+ # cycle
+ c[csr_cycle] = csr_output_value.eq(minfo.cycle_counter[0:32])
+ c[csr_cycleh] = csr_output_value.eq(minfo.cycle_counter[32:64])
+ # time
+ c[csr_time] = csr_output_value.eq(minfo.time_counter[0:32])
+ c[csr_timeh] = csr_output_value.eq(minfo.time_counter[32:64])
+ # instret
+ c[csr_instret] = csr_output_value.eq(minfo.instret_counter[0:32])
+ c[csr_instreth] = csr_output_value.eq(minfo.instret_counter[32:64])
+ # mvendorid/march/mimpl/mhart
+ c[csr_mvendorid] = csr_output_value.eq(minfo.mvendorid)
+ c[csr_marchid ] = csr_output_value.eq(minfo.marchid )
+ c[csr_mimpid ] = csr_output_value.eq(minfo.mimpid )
+ c[csr_mhartid ] = csr_output_value.eq(minfo.mhartid )
+ # misa
+ c[csr_misa ] = csr_output_value.eq(misa.misa)
+ # mstatus
+ c[csr_mstatus ] = [
+ csr_output_value.eq(mstatus.make()),
+ csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
+ csr_written_value),
+ mstatus.mpie.eq(csr_written_value[7]),
+ mstatus.mie.eq(csr_written_value[3])
+ ]
+ # mie
+ c[csr_mie ] = [
+ csr_output_value.eq(mie.make()),
+ csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
+ csr_written_value),
+ mie.meie.eq(csr_written_value[11]),
+ mie.mtie.eq(csr_written_value[7]),
+ mie.msie.eq(csr_written_value[3]),
+ ]
+ # mtvec
+ c[csr_mtvec ] = csr_output_value.eq(mtvec)
+ # mscratch
+ c[csr_mscratch ] = [
+ csr_output_value.eq(m.mscratch),
+ csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
+ csr_written_value),
+ If(csr.writes,
+ m.mscratch.eq(csr_written_value),
+ )
+ ]
+ # mepc
+ c[csr_mepc ] = [
+ csr_output_value.eq(m.mepc),
+ csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
+ csr_written_value),
+ If(csr.writes,
+ m.mepc.eq(csr_written_value),
+ )
+ ]
+
+ # mcause
+ c[csr_mcause ] = [
+ csr_output_value.eq(m.mcause),
+ csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
+ csr_written_value),
+ If(csr.writes,
+ m.mcause.eq(csr_written_value),
+ )
+ ]
+
+ # mip
+ c[csr_mip ] = [
+ csr_output_value.eq(mip.make()),
+ csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
+ csr_written_value),
+ ]
+
+ return [Case(csr.number, c),
+ If(csr.reads,
+ self.write_register(dc.rd, csr_output_value)
+ )]
+
+ """
+ `csr_mip: begin
+ csr_output_value = 0;
+ csr_output_value[11] = mip_meip;
+ csr_output_value[9] = mip_seip;
+ csr_output_value[8] = mip_ueip;
+ csr_output_value[7] = mip_mtip;
+ csr_output_value[5] = mip_stip;
+ csr_output_value[4] = mip_utip;
+ csr_output_value[3] = mip_msip;
+ csr_output_value[1] = mip_ssip;
+ csr_output_value[0] = mip_usip;
+ end
+ endcase
+ end
+ endcase
+ end
+ """
def __init__(self):
self.clk = ClockSignal()
self.reset = ResetSignal()
misaligned_jump_target = Signal()
self.comb += misaligned_jump_target.eq(ft.target_pc[1])
-
+
branch_arg_a = Signal(32)
branch_arg_b = Signal(32)
self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
m = M(self.comb, self.sync)
mstatus = MStatus(self.comb, self.sync)
mie = MIE(self.comb, self.sync)
-
misa = Misa(self.comb, self.sync)
-
- mvendorid = Signal(32)
- marchid = Signal(32)
- mimpid = Signal(32)
- mhartid = Signal(32)
- self.comb += mvendorid.eq(Constant(0, 32))
- self.comb += marchid.eq(Constant(0, 32))
- self.comb += mimpid.eq(Constant(0, 32))
- self.comb += mhartid.eq(Constant(0, 32))
-
mip = MIP(self.comb, self.sync)
- csr_op_is_valid = Signal()
+ # CSR decoding
+ csr = CSR(self.comb, self.sync, dc, register_rs1)
self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
branch_taken, misaligned_jump_target,
- csr_op_is_valid)
-
- #self.comb += self.handle_trap(m, mstatus, ft, dc, load_store_misaligned)
- # CSR decoding
- csr_number = Signal(12)
- csr_input_value = Signal(32)
- csr_reads = Signal()
- csr_writes = Signal()
+ csr.op_is_valid)
- self.comb += csr_number.eq(dc.immediate)
- self.comb += csr_input_value.eq(Mux(dc.funct3[2],
- dc.rs1,
- register_rs1))
- self.comb += csr_reads.eq(dc.funct3[1] | (dc.rd != 0))
- self.comb += csr_writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
+ minfo = MInfo(self.comb)
- self.comb += self.get_csr_op_is_valid(csr_op_is_valid, csr_number,
- csr_reads, csr_writes)
+ self.sync += If(~self.reset,
+ self.main_block(mtvec, mip, minfo, misa, csr, mi, m,
+ mstatus, mie, ft, dc,
+ load_store_misaligned,
+ loaded_value,
+ alu_result,
+ lui_auipc_result)
+ )
if __name__ == "__main__":
example = CPU()
"""
- wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
- wire [63:0] time_counter = 0; // TODO: implement time_counter
- wire [63:0] instret_counter = 0; // TODO: implement instret_counter
-
always @(posedge clk) begin:main_block
if(reset) begin
reset_to_initial();