self.clk = ClockSignal()
self.reset = ResetSignal()
#output [31:2] memory_interface_fetch_address,
- self.memory_interface_fetch_address = Signal(32)[2:]
+ self.memory_interface_fetch_address = Signal(32)
#input [31:0] memory_interface_fetch_data,
self.memory_interface_fetch_data = Signal(32)
self.memory_interface_fetch_valid = Signal()
fetch_pc = Signal(32, reset=reset_vector)
- self.sync += If(fetch_action != fetch_action_wait,
+ self.sync += If(self.fetch_action != fetch_action_wait,
self.output_pc.eq(fetch_pc))
- memory_interface_fetch_address = fetch_pc[2:]
+ self.comb += self.memory_interface_fetch_address.eq(fetch_pc[2:])
#initial output_pc <= reset_vector;
#initial output_state <= `fetch_output_state_empty;
delayed_instruction_valid = Signal(reset=0)
self.sync += delayed_instruction.eq(self.output_instruction)
- self.sync += self.output_state.eq(fetch_output_state_empty)
self.comb += If(delayed_instruction_valid,
self.output_instruction.eq(delayed_instruction)
self.output_instruction.eq(self.memory_interface_fetch_data)
)
- self.sync += delayed_instruction_valid.eq(fetch_action ==
+ self.sync += delayed_instruction_valid.eq(self.fetch_action ==
fetch_action_wait)
fc = {
}
fc[fetch_action_default] = fc[fetch_action_ack_trap]
fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
- self.sync += Case(fetch_action, fc).makedefault(fetch_action_default)
+ self.sync += Case(self.fetch_action,
+ fc).makedefault(fetch_action_default)
if __name__ == "__main__":
example = CPUFetchStage()
- memory_interface_fetch_address = Signal(32)
+ #memory_interface_fetch_address = Signal(32)
print(verilog.convert(example,
{ #example.clk,
#example.reset,
- memory_interface_fetch_address,
+ example.memory_interface_fetch_address,
example.memory_interface_fetch_data,
example.memory_interface_fetch_valid,
example.fetch_action,