use work.common.all;
entity cr_file is
+ generic (
+ SIM : boolean := false;
+ -- Non-zero to enable log data collection
+ LOG_LENGTH : natural := 0
+ );
port(
clk : in std_logic;
d_in : in Decode2ToCrFileType;
d_out : out CrFileToDecode2Type;
- w_in : in WritebackToCrFileType
+ w_in : in WritebackToCrFileType;
+
+ -- debug
+ sim_dump : in std_ulogic;
+
+ log_out : out std_ulogic_vector(12 downto 0)
);
end entity cr_file;
d_out.read_cr_data <= crs_updated;
d_out.read_xerc_data <= xerc_updated;
end process;
+
+ sim_dump_test: if SIM generate
+ dump_cr: process(all)
+ begin
+ if sim_dump = '1' then
+ report "CR 00000000" & to_hstring(crs);
+ assert false report "end of test" severity failure;
+ end if;
+ end process;
+ end generate;
+
+ cf_log: if LOG_LENGTH > 0 generate
+ signal log_data : std_ulogic_vector(12 downto 0);
+ begin
+ cr_log: process(clk)
+ begin
+ if rising_edge(clk) then
+ log_data <= w_in.write_cr_enable &
+ w_in.write_cr_data(31 downto 28) &
+ w_in.write_cr_mask;
+ end if;
+ end process;
+ log_out <= log_data;
+ end generate;
+
end architecture behaviour;