mw_debug: Fix memory overflow with "sim" backend

[microwatt.git] / cr_hazard.vhdl

diff --git a/cr_hazard.vhdl b/cr_hazard.vhdl
index 2a434ac6b07f4bf069b6c878a5582b0f270b8ad0..f6c5f3fa197e94517a36e5937136c6b971734052 100644 (file)
--- a/cr_hazard.vhdl
+++ b/cr_hazard.vhdl
@@ -7,7 +7,8 @@ entity cr_hazard is
         PIPELINE_DEPTH : natural := 2
         );
     port(
-        clk         : in std_logic;
+        clk         : in std_ulogic;
+       stall_in    : in std_ulogic;
 
         cr_read_in  : in std_ulogic;
         cr_write_in : in std_ulogic;
@@ -29,7 +30,9 @@ begin
     cr_hazard0: process(clk)
     begin
         if rising_edge(clk) then
-            r <= rin;
+           if stall_in = '0' then
+               r <= rin;
+           end if;
         end if;
     end process;