# Crypto-router ASIC
+<img src="https://www.ngi.eu/wp-content/uploads/sites/48/2020/04/Logo_Pointer.png" width="200px" />
+<img src="https://ngi.eu/wp-content/uploads/sites/77/2017/10/bandiera_stelle.png" width="50px" /><span> </span>
+<img src="https://nlnet.nl/image/logos/NGIAssure_tag.svg" width="130px" />
+<span> </span>
+<img src="https://www.artandtechnology.nl/logo.jpg" width="130px" />
+
+**This project has received funding from the European Union’s Horizon 2020 research and innovation programme within the framework of the NGI-POINTER Project funded under grant agreement No 871528**
+
+**This project has received funding from the European Union’s Horizon 2020 research and innovation programme within the framework of the NGI-ASSURE Project funded under grant agreement No 957073.**
+
* NLnet page: [[nlnet_2021_crypto_router]]
* Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>
+* ASIC/IO Pin specification page: [[crypto_router_asic/crypto_router_pinspec]]
# Specifications
OpenPOWER CPU with
[[openpower/sv/bitmanip]] extensions
* 180/130 nm (TBD)
-* 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs
+* 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs with
+ [SRAM](https://github.com/adamgreig/daqnet/blob/master/gateware/daqnet/ethernet/rmii.py)
+ on-chip, built-in.
* 2x USB [[shakti/m_class/ULPI]] PHYs
* Direct DMA interface (independent bulk transfer)
* [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),
Example [bpermd proof](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD)
and individual unit tests for the
[Logical pipeline](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/test/test_pipe_caller.py;hb=HEAD)
-* [Litex sim.py](https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;hb=HEAD)
+* simulation
with some peripherals developed in c++ as verilator modules
* nmigen-based OpenPOWER Libre-SOC core co-simulation such as
this unit test,