complete_in : in std_ulogic;
stall_out : out std_ulogic;
+ stopped_out : out std_ulogic;
+
flush_in: in std_ulogic;
d_in : in Decode1ToDecode2Type;
e_out : out Decode2ToExecute1Type;
m_out : out Decode2ToMultiplyType;
+ d_out : out Decode2ToDividerType;
l_out : out Decode2ToLoadstore1Type;
r_in : in RegisterFileToDecode2Type;
end entity decode2;
architecture behaviour of decode2 is
- type state_type is (IDLE, WAIT_FOR_PREV_TO_COMPLETE, WAIT_FOR_CURR_TO_COMPLETE);
-
- type reg_internal_type is record
- state : state_type;
- outstanding : integer;
- end record;
-
type reg_type is record
e : Decode2ToExecute1Type;
m : Decode2ToMultiplyType;
+ d : Decode2ToDividerType;
l : Decode2ToLoadstore1Type;
end record;
- signal r_int, rin_int : reg_internal_type;
signal r, rin : reg_type;
type decode_input_reg_t is record
function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
+ variable is_reg : std_ulogic;
begin
- case t is
- when RA =>
+ is_reg := '0' when insn_ra(insn_in) = "00000" else '1';
+
+ if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
+ --return (is_reg, insn_ra(insn_in), reg_data);
return ('1', insn_ra(insn_in), reg_data);
- when RA_OR_ZERO =>
- return ('1', insn_ra(insn_in), ra_or_zero(reg_data, insn_ra(insn_in)));
- when RS =>
- return ('1', insn_rs(insn_in), reg_data);
- when NONE =>
+ else
return ('0', (others => '0'), (others => '0'));
- end case;
+ end if;
end;
function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
case t is
when RB =>
return ('1', insn_rb(insn_in), reg_data);
- when RS =>
- return ('1', insn_rs(insn_in), reg_data);
when CONST_UI =>
return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
when CONST_SI =>
return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
when CONST_DS =>
return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
+ when CONST_M1 =>
+ return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
+ when CONST_SH =>
+ return ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
+ when CONST_SH32 =>
+ return ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
when NONE =>
return ('0', (others => '0'), (others => '0'));
end case;
end case;
end;
- function decode_const_a (t : constant_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
- begin
- case t is
- when SH =>
- return "00" & insn_sh(insn_in);
- when SH32 =>
- return "000" & insn_sh32(insn_in);
- when FXM =>
- return insn_fxm(insn_in);
- when BO =>
- return "000" & insn_bo(insn_in);
- when BF =>
- return "00000" & insn_bf(insn_in);
- when TOO =>
- return "000" & insn_to(insn_in);
- when BC =>
- return "000" & insn_bc(insn_in);
- when NONE =>
- return "00000000";
- end case;
- end;
-
- function decode_const_b (t : constant_b_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
- begin
- case t is
- when MB =>
- return insn_mb(insn_in);
- when ME =>
- return insn_me(insn_in);
- when MB32 =>
- return "0" & insn_mb32(insn_in);
- when BI =>
- return "0" & insn_bi(insn_in);
- when L =>
- return "00000" & insn_l(insn_in);
- when NONE =>
- return "000000";
- end case;
- end;
-
- function decode_const_c (t : constant_c_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
- begin
- case t is
- when ME32 =>
- return insn_me32(insn_in);
- when BH =>
- return "000" & insn_bh(insn_in);
- when NONE =>
- return "00000";
- end case;
- end;
-
function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
begin
case t is
return '0';
end case;
end;
+
+ -- issue control signals
+ signal control_valid_in : std_ulogic;
+ signal control_valid_out : std_ulogic;
+ signal control_sgl_pipe : std_logic;
+
+ signal gpr_write_valid : std_ulogic;
+ signal gpr_write : std_ulogic_vector(4 downto 0);
+
+ signal gpr_a_read_valid : std_ulogic;
+ signal gpr_a_read : std_ulogic_vector(4 downto 0);
+
+ signal gpr_b_read_valid : std_ulogic;
+ signal gpr_b_read : std_ulogic_vector(4 downto 0);
+
+ signal gpr_c_read_valid : std_ulogic;
+ signal gpr_c_read : std_ulogic_vector(4 downto 0);
+
+ signal cr_write_valid : std_ulogic;
begin
+ control_0: entity work.control
+ generic map (
+ PIPELINE_DEPTH => 2
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ complete_in => complete_in,
+ valid_in => control_valid_in,
+ flush_in => flush_in,
+ sgl_pipe_in => control_sgl_pipe,
+ stop_mark_in => d_in.stop_mark,
+
+ gpr_write_valid_in => gpr_write_valid,
+ gpr_write_in => gpr_write,
+
+ gpr_a_read_valid_in => gpr_a_read_valid,
+ gpr_a_read_in => gpr_a_read,
+
+ gpr_b_read_valid_in => gpr_b_read_valid,
+ gpr_b_read_in => gpr_b_read,
+
+ gpr_c_read_valid_in => gpr_c_read_valid,
+ gpr_c_read_in => gpr_c_read,
+
+ cr_read_in => d_in.decode.input_cr,
+ cr_write_in => cr_write_valid,
+
+ valid_out => control_valid_out,
+ stall_out => stall_out,
+ stopped_out => stopped_out
+ );
decode2_0: process(clk)
begin
if rising_edge(clk) then
- if rin.e.valid = '1' then
- report "execute " & to_hstring(rin.e.nia);
- end if;
- if rin.l.valid = '1' then
- report "execute " & to_hstring(rin.e.nia);
- end if;
- if rin.m.valid = '1' then
+ if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' or rin.d.valid = '1' then
report "execute " & to_hstring(rin.e.nia);
end if;
r <= rin;
- r_int <= rin_int;
end if;
end process;
- r_out.read1_reg <= insn_ra(d_in.insn) when (d_in.decode.input_reg_a = RA) else
- insn_ra(d_in.insn) when d_in.decode.input_reg_a = RA_OR_ZERO else
- insn_rs(d_in.insn) when d_in.decode.input_reg_a = RS else
- (others => '0');
-
- r_out.read2_reg <= insn_rb(d_in.insn) when d_in.decode.input_reg_b = RB else
- insn_rs(d_in.insn) when d_in.decode.input_reg_b = RS else
- (others => '0');
-
- r_out.read3_reg <= insn_rs(d_in.insn) when d_in.decode.input_reg_c = RS else
- (others => '0');
+ r_out.read1_reg <= insn_ra(d_in.insn);
+ r_out.read2_reg <= insn_rb(d_in.insn);
+ r_out.read3_reg <= insn_rs(d_in.insn);
c_out.read <= d_in.decode.input_cr;
decode2_1: process(all)
variable v : reg_type;
- variable v_int : reg_internal_type;
variable mul_a : std_ulogic_vector(63 downto 0);
variable mul_b : std_ulogic_vector(63 downto 0);
variable decoded_reg_a : decode_input_reg_t;
variable decoded_reg_b : decode_input_reg_t;
variable decoded_reg_c : decode_input_reg_t;
- variable is_valid : std_ulogic;
+ variable signed_division: std_ulogic;
+ variable length : std_ulogic_vector(3 downto 0);
begin
v := r;
- v_int := r_int;
v.e := Decode2ToExecute1Init;
v.l := Decode2ToLoadStore1Init;
v.m := Decode2ToMultiplyInit;
+ v.d := Decode2ToDividerInit;
mul_a := (others => '0');
mul_b := (others => '0');
r_out.read2_enable <= decoded_reg_b.reg_valid;
r_out.read3_enable <= decoded_reg_c.reg_valid;
+ case d_in.decode.length is
+ when is1B =>
+ length := "0001";
+ when is2B =>
+ length := "0010";
+ when is4B =>
+ length := "0100";
+ when is8B =>
+ length := "1000";
+ when NONE =>
+ length := "0000";
+ end case;
+
-- execute unit
v.e.nia := d_in.nia;
v.e.insn_type := d_in.decode.insn_type;
v.e.read_data1 := decoded_reg_a.data;
v.e.read_reg2 := decoded_reg_b.reg;
v.e.read_data2 := decoded_reg_b.data;
+ v.e.read_data3 := decoded_reg_c.data;
v.e.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
v.e.cr := c_in.read_cr_data;
+ v.e.invert_a := d_in.decode.invert_a;
+ v.e.invert_out := d_in.decode.invert_out;
v.e.input_carry := d_in.decode.input_carry;
v.e.output_carry := d_in.decode.output_carry;
+ v.e.is_32bit := d_in.decode.is_32bit;
+ v.e.is_signed := d_in.decode.is_signed;
if d_in.decode.lr = '1' then
v.e.lr := insn_lk(d_in.insn);
end if;
- v.e.const1 := decode_const_a(d_in.decode.const_a, d_in.insn);
- v.e.const2 := decode_const_b(d_in.decode.const_b, d_in.insn);
- v.e.const3 := decode_const_c(d_in.decode.const_c, d_in.insn);
+ v.e.insn := d_in.insn;
+ v.e.data_len := length;
-- multiply unit
- v.m.nia := d_in.nia;
v.m.insn_type := d_in.decode.insn_type;
mul_a := decoded_reg_a.data;
mul_b := decoded_reg_b.data;
v.m.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
v.m.rc := decode_rc(d_in.decode.rc, d_in.insn);
- if d_in.decode.mul_32bit = '1' then
- if d_in.decode.mul_signed = '1' then
+ if d_in.decode.is_32bit = '1' then
+ if d_in.decode.is_signed = '1' then
v.m.data1 := (others => mul_a(31));
v.m.data1(31 downto 0) := mul_a(31 downto 0);
v.m.data2 := (others => mul_b(31));
v.m.data2 := '0' & x"00000000" & mul_b(31 downto 0);
end if;
else
- if d_in.decode.mul_signed = '1' then
+ if d_in.decode.is_signed = '1' then
v.m.data1 := mul_a(63) & mul_a;
v.m.data2 := mul_b(63) & mul_b;
else
end if;
end if;
+ -- divide unit
+ -- PPC divide and modulus instruction words have these bits in
+ -- the bottom 11 bits: o1dns 010t1 r
+ -- where o = OE for div instrs, signedness for mod instrs
+ -- d = 1 for div*, 0 for mod*
+ -- n = 1 for normal, 0 for extended (dividend << 32/64)
+ -- s = 1 for signed, 0 for unsigned (for div*)
+ -- t = 1 for 32-bit, 0 for 64-bit
+ -- r = RC bit (record condition code)
+ v.d.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
+ v.d.is_modulus := not d_in.insn(8);
+ v.d.is_32bit := d_in.insn(2);
+ if d_in.insn(8) = '1' then
+ signed_division := d_in.insn(6);
+ else
+ signed_division := d_in.insn(10);
+ end if;
+ v.d.is_signed := signed_division;
+ if d_in.insn(2) = '0' then
+ -- 64-bit forms
+ if d_in.insn(8) = '1' and d_in.insn(7) = '0' then
+ v.d.is_extended := '1';
+ end if;
+ v.d.dividend := decoded_reg_a.data;
+ v.d.divisor := decoded_reg_b.data;
+ else
+ -- 32-bit forms
+ if d_in.insn(8) = '1' and d_in.insn(7) = '0' then -- extended forms
+ v.d.dividend := decoded_reg_a.data(31 downto 0) & x"00000000";
+ elsif signed_division = '1' and decoded_reg_a.data(31) = '1' then
+ -- sign extend to 64 bits
+ v.d.dividend := x"ffffffff" & decoded_reg_a.data(31 downto 0);
+ else
+ v.d.dividend := x"00000000" & decoded_reg_a.data(31 downto 0);
+ end if;
+ if signed_division = '1' and decoded_reg_b.data(31) = '1' then
+ v.d.divisor := x"ffffffff" & decoded_reg_b.data(31 downto 0);
+ else
+ v.d.divisor := x"00000000" & decoded_reg_b.data(31 downto 0);
+ end if;
+ end if;
+ v.d.rc := decode_rc(d_in.decode.rc, d_in.insn);
+
-- load/store unit
- v.l.nia := d_in.nia;
v.l.update_reg := decoded_reg_a.reg;
v.l.addr1 := decoded_reg_a.data;
v.l.addr2 := decoded_reg_b.data;
v.l.load := '0';
end if;
- case d_in.decode.length is
- when is1B =>
- v.l.length := "0001";
- when is2B =>
- v.l.length := "0010";
- when is4B =>
- v.l.length := "0100";
- when is8B =>
- v.l.length := "1000";
- when NONE =>
- v.l.length := "0000";
- end case;
-
+ v.l.length := length;
v.l.byte_reverse := d_in.decode.byte_reverse;
v.l.sign_extend := d_in.decode.sign_extend;
v.l.update := d_in.decode.update;
- -- single issue
+ -- issue control
+ control_valid_in <= d_in.valid;
+ control_sgl_pipe <= d_in.decode.sgl_pipe;
- if complete_in = '1' then
- v_int.outstanding := v_int.outstanding - 1;
- end if;
+ gpr_write_valid <= '1' when d_in.decode.output_reg_a /= NONE else '0';
+ gpr_write <= decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
- -- state machine to handle instructions that must be single
- -- through the pipeline.
- stall_out <= '0';
- is_valid := d_in.valid;
- case v_int.state is
- when IDLE =>
- if (flush_in = '0') and (d_in.valid = '1') and (d_in.decode.sgl_pipe = '1') then
- if v_int.outstanding /= 0 then
- v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
- stall_out <= '1';
- is_valid := '0';
- else
- -- send insn out and wait on it to complete
- v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
- end if;
- end if;
+ gpr_a_read_valid <= decoded_reg_a.reg_valid;
+ gpr_a_read <= decoded_reg_a.reg;
- when WAIT_FOR_PREV_TO_COMPLETE =>
- if v_int.outstanding = 0 then
- -- send insn out and wait on it to complete
- v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
- else
- stall_out <= '1';
- is_valid := '0';
- end if;
+ gpr_b_read_valid <= decoded_reg_b.reg_valid;
+ gpr_b_read <= decoded_reg_b.reg;
- when WAIT_FOR_CURR_TO_COMPLETE =>
- if v_int.outstanding = 0 then
- v_int.state := IDLE;
- else
- stall_out <= '1';
- is_valid := '0';
- end if;
- end case;
+ gpr_c_read_valid <= decoded_reg_c.reg_valid;
+ gpr_c_read <= decoded_reg_c.reg;
+
+ cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
v.e.valid := '0';
v.m.valid := '0';
+ v.d.valid := '0';
v.l.valid := '0';
case d_in.decode.unit is
when ALU =>
- v.e.valid := is_valid;
+ v.e.valid := control_valid_out;
when LDST =>
- v.l.valid := is_valid;
+ v.l.valid := control_valid_out;
when MUL =>
- v.m.valid := is_valid;
+ v.m.valid := control_valid_out;
+ when DIV =>
+ v.d.valid := control_valid_out;
when NONE =>
- v.e.valid := is_valid;
+ v.e.valid := control_valid_out;
v.e.insn_type := OP_ILLEGAL;
end case;
- if flush_in = '1' then
- v.e.valid := '0';
- v.m.valid := '0';
- v.l.valid := '0';
- end if;
-
- -- track outstanding instructions
- if v.e.valid = '1' or v.l.valid = '1' or v.m.valid = '1' then
- v_int.outstanding := v_int.outstanding + 1;
- end if;
-
- assert r_int.outstanding <= 1 report "Outstanding bad " & integer'image(r_int.outstanding) severity failure;
-
if rst = '1' then
- v_int.state := IDLE;
- v_int.outstanding := 0;
v.e := Decode2ToExecute1Init;
v.l := Decode2ToLoadStore1Init;
v.m := Decode2ToMultiplyInit;
+ v.d := Decode2ToDividerInit;
end if;
-- Update registers
rin <= v;
- rin_int <= v_int;
-- Update outputs
e_out <= r.e;
l_out <= r.l;
m_out <= r.m;
+ d_out <= r.d;
end process;
end architecture behaviour;
projects / microwatt.git / blobdiff