end entity decode2;
architecture behaviour of decode2 is
- type state_type is (IDLE, WAIT_FOR_PREV_TO_COMPLETE, WAIT_FOR_CURR_TO_COMPLETE);
-
- type reg_internal_type is record
- state : state_type;
- outstanding : integer;
- end record;
-
type reg_type is record
e : Decode2ToExecute1Type;
m : Decode2ToMultiplyType;
l : Decode2ToLoadstore1Type;
end record;
- signal r_int, rin_int : reg_internal_type;
signal r, rin : reg_type;
type decode_input_reg_t is record
function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
+ variable is_reg : std_ulogic;
begin
+ is_reg := '0' when insn_ra(insn_in) = "00000" else '1';
+
if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
+ --return (is_reg, insn_ra(insn_in), reg_data);
return ('1', insn_ra(insn_in), reg_data);
else
return ('0', (others => '0'), (others => '0'));
return '0';
end case;
end;
+
+ -- issue control signals
+ signal control_valid_in : std_ulogic;
+ signal control_valid_out : std_ulogic;
+ signal control_sgl_pipe : std_logic;
+
+ signal gpr_write_valid : std_ulogic;
+ signal gpr_write : std_ulogic_vector(4 downto 0);
+
+ signal gpr_a_read_valid : std_ulogic;
+ signal gpr_a_read : std_ulogic_vector(4 downto 0);
+
+ signal gpr_b_read_valid : std_ulogic;
+ signal gpr_b_read : std_ulogic_vector(4 downto 0);
+
+ signal gpr_c_read_valid : std_ulogic;
+ signal gpr_c_read : std_ulogic_vector(4 downto 0);
+
+ signal cr_write_valid : std_ulogic;
begin
+ control_0: entity work.control
+ generic map (
+ PIPELINE_DEPTH => 2
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ complete_in => complete_in,
+ valid_in => control_valid_in,
+ flush_in => flush_in,
+ sgl_pipe_in => control_sgl_pipe,
+ stop_mark_in => d_in.stop_mark,
+
+ gpr_write_valid_in => gpr_write_valid,
+ gpr_write_in => gpr_write,
+
+ gpr_a_read_valid_in => gpr_a_read_valid,
+ gpr_a_read_in => gpr_a_read,
+
+ gpr_b_read_valid_in => gpr_b_read_valid,
+ gpr_b_read_in => gpr_b_read,
+
+ gpr_c_read_valid_in => gpr_c_read_valid,
+ gpr_c_read_in => gpr_c_read,
+
+ cr_read_in => d_in.decode.input_cr,
+ cr_write_in => cr_write_valid,
+
+ valid_out => control_valid_out,
+ stall_out => stall_out,
+ stopped_out => stopped_out
+ );
decode2_0: process(clk)
begin
if rising_edge(clk) then
- assert r_int.outstanding <= 1 report "Outstanding bad " & integer'image(r_int.outstanding) severity failure;
-
if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' or rin.d.valid = '1' then
report "execute " & to_hstring(rin.e.nia);
end if;
r <= rin;
- r_int <= rin_int;
end if;
end process;
decode2_1: process(all)
variable v : reg_type;
- variable v_int : reg_internal_type;
variable mul_a : std_ulogic_vector(63 downto 0);
variable mul_b : std_ulogic_vector(63 downto 0);
variable decoded_reg_a : decode_input_reg_t;
variable decoded_reg_b : decode_input_reg_t;
variable decoded_reg_c : decode_input_reg_t;
variable signed_division: std_ulogic;
- variable is_valid : std_ulogic;
+ variable length : std_ulogic_vector(3 downto 0);
begin
v := r;
- v_int := r_int;
v.e := Decode2ToExecute1Init;
v.l := Decode2ToLoadStore1Init;
r_out.read2_enable <= decoded_reg_b.reg_valid;
r_out.read3_enable <= decoded_reg_c.reg_valid;
+ case d_in.decode.length is
+ when is1B =>
+ length := "0001";
+ when is2B =>
+ length := "0010";
+ when is4B =>
+ length := "0100";
+ when is8B =>
+ length := "1000";
+ when NONE =>
+ length := "0000";
+ end case;
+
-- execute unit
v.e.nia := d_in.nia;
v.e.insn_type := d_in.decode.insn_type;
v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
v.e.cr := c_in.read_cr_data;
v.e.invert_a := d_in.decode.invert_a;
+ v.e.invert_out := d_in.decode.invert_out;
v.e.input_carry := d_in.decode.input_carry;
v.e.output_carry := d_in.decode.output_carry;
v.e.is_32bit := d_in.decode.is_32bit;
v.e.lr := insn_lk(d_in.insn);
end if;
v.e.insn := d_in.insn;
+ v.e.data_len := length;
-- multiply unit
v.m.insn_type := d_in.decode.insn_type;
-- r = RC bit (record condition code)
v.d.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
v.d.is_modulus := not d_in.insn(8);
- v.d.is_32bit := not d_in.insn(2);
+ v.d.is_32bit := d_in.insn(2);
if d_in.insn(8) = '1' then
signed_division := d_in.insn(6);
else
v.l.load := '0';
end if;
- case d_in.decode.length is
- when is1B =>
- v.l.length := "0001";
- when is2B =>
- v.l.length := "0010";
- when is4B =>
- v.l.length := "0100";
- when is8B =>
- v.l.length := "1000";
- when NONE =>
- v.l.length := "0000";
- end case;
-
+ v.l.length := length;
v.l.byte_reverse := d_in.decode.byte_reverse;
v.l.sign_extend := d_in.decode.sign_extend;
v.l.update := d_in.decode.update;
- -- single issue
+ -- issue control
+ control_valid_in <= d_in.valid;
+ control_sgl_pipe <= d_in.decode.sgl_pipe;
- if complete_in = '1' then
- v_int.outstanding := v_int.outstanding - 1;
- end if;
+ gpr_write_valid <= '1' when d_in.decode.output_reg_a /= NONE else '0';
+ gpr_write <= decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
- -- state machine to handle instructions that must be single
- -- through the pipeline.
- stall_out <= '0';
- is_valid := d_in.valid;
-
- -- Handle debugger stop
- stopped_out <= '0';
- if d_in.stop_mark = '1' and v_int.outstanding = 0 then
- stopped_out <= '1';
- end if;
+ gpr_a_read_valid <= decoded_reg_a.reg_valid;
+ gpr_a_read <= decoded_reg_a.reg;
- case v_int.state is
- when IDLE =>
- if (flush_in = '0') and (is_valid = '1') and (d_in.decode.sgl_pipe = '1') then
- if v_int.outstanding /= 0 then
- v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
- stall_out <= '1';
- is_valid := '0';
- else
- -- send insn out and wait on it to complete
- v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
- end if;
- end if;
+ gpr_b_read_valid <= decoded_reg_b.reg_valid;
+ gpr_b_read <= decoded_reg_b.reg;
- when WAIT_FOR_PREV_TO_COMPLETE =>
- if v_int.outstanding = 0 then
- -- send insn out and wait on it to complete
- v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
- else
- stall_out <= '1';
- is_valid := '0';
- end if;
+ gpr_c_read_valid <= decoded_reg_c.reg_valid;
+ gpr_c_read <= decoded_reg_c.reg;
- when WAIT_FOR_CURR_TO_COMPLETE =>
- if v_int.outstanding = 0 then
- v_int.state := IDLE;
- else
- stall_out <= '1';
- is_valid := '0';
- end if;
- end case;
+ cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
v.e.valid := '0';
v.m.valid := '0';
v.l.valid := '0';
case d_in.decode.unit is
when ALU =>
- v.e.valid := is_valid;
+ v.e.valid := control_valid_out;
when LDST =>
- v.l.valid := is_valid;
+ v.l.valid := control_valid_out;
when MUL =>
- v.m.valid := is_valid;
+ v.m.valid := control_valid_out;
when DIV =>
- v.d.valid := is_valid;
+ v.d.valid := control_valid_out;
when NONE =>
- v.e.valid := is_valid;
+ v.e.valid := control_valid_out;
v.e.insn_type := OP_ILLEGAL;
end case;
- if flush_in = '1' then
- v.e.valid := '0';
- v.m.valid := '0';
- v.d.valid := '0';
- v.l.valid := '0';
- end if;
-
- -- track outstanding instructions
- if v.e.valid = '1' or v.l.valid = '1' or v.m.valid = '1' or v.d.valid = '1' then
- v_int.outstanding := v_int.outstanding + 1;
- end if;
-
if rst = '1' then
- v_int.state := IDLE;
- v_int.outstanding := 0;
v.e := Decode2ToExecute1Init;
v.l := Decode2ToLoadStore1Init;
v.m := Decode2ToMultiplyInit;
-- Update registers
rin <= v;
- rin_int <= v_int;
-- Update outputs
e_out <= r.e;
projects / microwatt.git / blobdiff