use work.insn_helpers.all;
entity decode2 is
+ generic (
+ EX1_BYPASS : boolean := true
+ );
port (
clk : in std_ulogic;
rst : in std_ulogic;
complete_in : in std_ulogic;
+ stall_in : in std_ulogic;
stall_out : out std_ulogic;
+ stopped_out : out std_ulogic;
+
flush_in: in std_ulogic;
d_in : in Decode1ToDecode2Type;
e_out : out Decode2ToExecute1Type;
- m_out : out Decode2ToMultiplyType;
- l_out : out Decode2ToLoadstore1Type;
r_in : in RegisterFileToDecode2Type;
r_out : out Decode2ToRegisterFileType;
end entity decode2;
architecture behaviour of decode2 is
- type state_type is (IDLE, WAIT_FOR_PREV_TO_COMPLETE, WAIT_FOR_CURR_TO_COMPLETE);
-
- type reg_internal_type is record
- state : state_type;
- outstanding : integer;
- end record;
-
type reg_type is record
e : Decode2ToExecute1Type;
- m : Decode2ToMultiplyType;
- l : Decode2ToLoadstore1Type;
end record;
- signal r_int, rin_int : reg_internal_type;
signal r, rin : reg_type;
type decode_input_reg_t is record
reg_valid : std_ulogic;
- reg : std_ulogic_vector(4 downto 0);
+ reg : gspr_index_t;
data : std_ulogic_vector(63 downto 0);
end record;
+ type decode_output_reg_t is record
+ reg_valid : std_ulogic;
+ reg : gspr_index_t;
+ end record;
+
function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
- reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
+ reg_data : std_ulogic_vector(63 downto 0);
+ ispr : gspr_index_t) return decode_input_reg_t is
begin
- case t is
- when RA =>
- return ('1', insn_ra(insn_in), reg_data);
- when RA_OR_ZERO =>
- return ('1', insn_ra(insn_in), ra_or_zero(reg_data, insn_ra(insn_in)));
- when RS =>
- return ('1', insn_rs(insn_in), reg_data);
- when NONE =>
+ if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
+ assert is_fast_spr(ispr) = '0' report "Decode A says GPR but ISPR says SPR:" &
+ to_hstring(ispr) severity failure;
+ return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
+ elsif t = SPR then
+ -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
+ -- If it's all 0, we don't treat it as a dependency as slow SPRs
+ -- operations are single issue.
+ --
+ assert is_fast_spr(ispr) = '1' or ispr = "000000"
+ report "Decode A says SPR but ISPR is invalid:" &
+ to_hstring(ispr) severity failure;
+ return (is_fast_spr(ispr), ispr, reg_data);
+ else
return ('0', (others => '0'), (others => '0'));
- end case;
+ end if;
end;
function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
- reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
+ reg_data : std_ulogic_vector(63 downto 0);
+ ispr : gspr_index_t) return decode_input_reg_t is
+ variable ret : decode_input_reg_t;
begin
case t is
when RB =>
- return ('1', insn_rb(insn_in), reg_data);
- when RS =>
- return ('1', insn_rs(insn_in), reg_data);
+ assert is_fast_spr(ispr) = '0' report "Decode B says GPR but ISPR says SPR:" &
+ to_hstring(ispr) severity failure;
+ ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
when CONST_UI =>
- return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
+ ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
when CONST_SI =>
- return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
+ ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
when CONST_SI_HI =>
- return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
+ ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
when CONST_UI_HI =>
- return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
+ ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
when CONST_LI =>
- return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
+ ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
when CONST_BD =>
- return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
+ ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
when CONST_DS =>
- return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
+ ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
+ when CONST_M1 =>
+ ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
+ when CONST_SH =>
+ ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
+ when CONST_SH32 =>
+ ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
+ when SPR =>
+ -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
+ -- If it's all 0, we don't treat it as a dependency as slow SPRs
+ -- operations are single issue.
+ assert is_fast_spr(ispr) = '1' or ispr = "000000"
+ report "Decode B says SPR but ISPR is invalid:" &
+ to_hstring(ispr) severity failure;
+ ret := (is_fast_spr(ispr), ispr, reg_data);
when NONE =>
- return ('0', (others => '0'), (others => '0'));
+ ret := ('0', (others => '0'), (others => '0'));
end case;
+
+ return ret;
end;
function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
begin
case t is
when RS =>
- return ('1', insn_rs(insn_in), reg_data);
+ return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
when NONE =>
return ('0', (others => '0'), (others => '0'));
end case;
end;
- function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
+ function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
+ ispr : gspr_index_t) return decode_output_reg_t is
begin
case t is
when RT =>
- return insn_rt(insn_in);
+ return ('1', gpr_to_gspr(insn_rt(insn_in)));
when RA =>
- return insn_ra(insn_in);
- when NONE =>
- return "00000";
- end case;
- end;
-
- function decode_const_a (t : constant_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
- begin
- case t is
- when SH =>
- return "00" & insn_sh(insn_in);
- when SH32 =>
- return "000" & insn_sh32(insn_in);
- when FXM =>
- return insn_fxm(insn_in);
- when BO =>
- return "000" & insn_bo(insn_in);
- when BF =>
- return "00000" & insn_bf(insn_in);
- when TOO =>
- return "000" & insn_to(insn_in);
- when BC =>
- return "000" & insn_bc(insn_in);
+ return ('1', gpr_to_gspr(insn_ra(insn_in)));
+ when SPR =>
+ -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
+ -- If it's all 0, we don't treat it as a dependency as slow SPRs
+ -- operations are single issue.
+ assert is_fast_spr(ispr) = '1' or ispr = "000000"
+ report "Decode B says SPR but ISPR is invalid:" &
+ to_hstring(ispr) severity failure;
+ return (is_fast_spr(ispr), ispr);
when NONE =>
- return "00000000";
+ return ('0', "000000");
end case;
end;
- function decode_const_b (t : constant_b_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
- begin
- case t is
- when MB =>
- return insn_mb(insn_in);
- when ME =>
- return insn_me(insn_in);
- when MB32 =>
- return "0" & insn_mb32(insn_in);
- when BI =>
- return "0" & insn_bi(insn_in);
- when L =>
- return "00000" & insn_l(insn_in);
- when NONE =>
- return "000000";
- end case;
- end;
-
- function decode_const_c (t : constant_c_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
+ function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
begin
case t is
- when ME32 =>
- return insn_me32(insn_in);
- when BH =>
- return "000" & insn_bh(insn_in);
+ when RC =>
+ return insn_rc(insn_in);
+ when ONE =>
+ return '1';
when NONE =>
- return "00000";
+ return '0';
end case;
end;
- function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
+ -- For now, use "rc" in the decode table to decide whether oe exists.
+ -- This is not entirely correct architecturally: For mulhd and
+ -- mulhdu, the OE field is reserved. It remains to be seen what an
+ -- actual POWER9 does if we set it on those instructions, for now we
+ -- test that further down when assigning to the multiplier oe input.
+ --
+ function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
begin
case t is
when RC =>
- return insn_rc(insn_in);
- when ONE =>
- return '1';
- when NONE =>
+ return insn_oe(insn_in);
+ when OTHERS =>
return '0';
end case;
end;
+
+ -- issue control signals
+ signal control_valid_in : std_ulogic;
+ signal control_valid_out : std_ulogic;
+ signal control_sgl_pipe : std_logic;
+
+ signal gpr_write_valid : std_ulogic;
+ signal gpr_write : gspr_index_t;
+ signal gpr_bypassable : std_ulogic;
+
+ signal gpr_a_read_valid : std_ulogic;
+ signal gpr_a_read :gspr_index_t;
+ signal gpr_a_bypass : std_ulogic;
+
+ signal gpr_b_read_valid : std_ulogic;
+ signal gpr_b_read : gspr_index_t;
+ signal gpr_b_bypass : std_ulogic;
+
+ signal gpr_c_read_valid : std_ulogic;
+ signal gpr_c_read : gpr_index_t;
+ signal gpr_c_bypass : std_ulogic;
+
+ signal cr_write_valid : std_ulogic;
begin
+ control_0: entity work.control
+ generic map (
+ PIPELINE_DEPTH => 1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ complete_in => complete_in,
+ valid_in => control_valid_in,
+ stall_in => stall_in,
+ flush_in => flush_in,
+ sgl_pipe_in => control_sgl_pipe,
+ stop_mark_in => d_in.stop_mark,
+
+ gpr_write_valid_in => gpr_write_valid,
+ gpr_write_in => gpr_write,
+ gpr_bypassable => gpr_bypassable,
+
+ gpr_a_read_valid_in => gpr_a_read_valid,
+ gpr_a_read_in => gpr_a_read,
+
+ gpr_b_read_valid_in => gpr_b_read_valid,
+ gpr_b_read_in => gpr_b_read,
+
+ gpr_c_read_valid_in => gpr_c_read_valid,
+ gpr_c_read_in => gpr_c_read,
+
+ cr_read_in => d_in.decode.input_cr,
+ cr_write_in => cr_write_valid,
+
+ valid_out => control_valid_out,
+ stall_out => stall_out,
+ stopped_out => stopped_out,
+
+ gpr_bypass_a => gpr_a_bypass,
+ gpr_bypass_b => gpr_b_bypass,
+ gpr_bypass_c => gpr_c_bypass
+ );
decode2_0: process(clk)
begin
if rising_edge(clk) then
- assert r_int.outstanding <= 1 report "Outstanding bad " & integer'image(r_int.outstanding) severity failure;
-
- if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' then
+ if rin.e.valid = '1' then
report "execute " & to_hstring(rin.e.nia);
end if;
r <= rin;
- r_int <= rin_int;
end if;
end process;
- r_out.read1_reg <= insn_ra(d_in.insn) when (d_in.decode.input_reg_a = RA) else
- insn_ra(d_in.insn) when d_in.decode.input_reg_a = RA_OR_ZERO else
- insn_rs(d_in.insn) when d_in.decode.input_reg_a = RS else
- (others => '0');
-
- r_out.read2_reg <= insn_rb(d_in.insn) when d_in.decode.input_reg_b = RB else
- insn_rs(d_in.insn) when d_in.decode.input_reg_b = RS else
- (others => '0');
-
- r_out.read3_reg <= insn_rs(d_in.insn) when d_in.decode.input_reg_c = RS else
- (others => '0');
+ r_out.read1_reg <= gpr_or_spr_to_gspr(insn_ra(d_in.insn), d_in.ispr1);
+ r_out.read2_reg <= gpr_or_spr_to_gspr(insn_rb(d_in.insn), d_in.ispr2);
+ r_out.read3_reg <= insn_rs(d_in.insn);
c_out.read <= d_in.decode.input_cr;
decode2_1: process(all)
variable v : reg_type;
- variable v_int : reg_internal_type;
variable mul_a : std_ulogic_vector(63 downto 0);
variable mul_b : std_ulogic_vector(63 downto 0);
variable decoded_reg_a : decode_input_reg_t;
variable decoded_reg_b : decode_input_reg_t;
variable decoded_reg_c : decode_input_reg_t;
- variable is_valid : std_ulogic;
+ variable decoded_reg_o : decode_output_reg_t;
+ variable length : std_ulogic_vector(3 downto 0);
begin
v := r;
- v_int := r_int;
v.e := Decode2ToExecute1Init;
- v.l := Decode2ToLoadStore1Init;
- v.m := Decode2ToMultiplyInit;
mul_a := (others => '0');
mul_b := (others => '0');
--v.e.input_cr := d_in.decode.input_cr;
- --v.m.input_cr := d_in.decode.input_cr;
--v.e.output_cr := d_in.decode.output_cr;
-
- decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data);
- decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data);
+
+ decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1);
+ decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
+ decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
r_out.read1_enable <= decoded_reg_a.reg_valid;
r_out.read2_enable <= decoded_reg_b.reg_valid;
r_out.read3_enable <= decoded_reg_c.reg_valid;
+ case d_in.decode.length is
+ when is1B =>
+ length := "0001";
+ when is2B =>
+ length := "0010";
+ when is4B =>
+ length := "0100";
+ when is8B =>
+ length := "1000";
+ when NONE =>
+ length := "0000";
+ end case;
+
-- execute unit
v.e.nia := d_in.nia;
v.e.insn_type := d_in.decode.insn_type;
v.e.read_reg1 := decoded_reg_a.reg;
v.e.read_data1 := decoded_reg_a.data;
+ v.e.bypass_data1 := gpr_a_bypass;
v.e.read_reg2 := decoded_reg_b.reg;
v.e.read_data2 := decoded_reg_b.data;
- v.e.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
+ v.e.bypass_data2 := gpr_b_bypass;
+ v.e.read_data3 := decoded_reg_c.data;
+ v.e.bypass_data3 := gpr_c_bypass;
+ v.e.write_reg := decoded_reg_o.reg;
v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
+ if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
+ v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
+ end if;
v.e.cr := c_in.read_cr_data;
+ v.e.xerc := c_in.read_xerc_data;
+ v.e.invert_a := d_in.decode.invert_a;
+ v.e.invert_out := d_in.decode.invert_out;
v.e.input_carry := d_in.decode.input_carry;
v.e.output_carry := d_in.decode.output_carry;
+ v.e.is_32bit := d_in.decode.is_32bit;
+ v.e.is_signed := d_in.decode.is_signed;
if d_in.decode.lr = '1' then
v.e.lr := insn_lk(d_in.insn);
end if;
- v.e.const1 := decode_const_a(d_in.decode.const_a, d_in.insn);
- v.e.const2 := decode_const_b(d_in.decode.const_b, d_in.insn);
- v.e.const3 := decode_const_c(d_in.decode.const_c, d_in.insn);
-
- -- multiply unit
- v.m.insn_type := d_in.decode.insn_type;
- mul_a := decoded_reg_a.data;
- mul_b := decoded_reg_b.data;
- v.m.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
- v.m.rc := decode_rc(d_in.decode.rc, d_in.insn);
-
- if d_in.decode.mul_32bit = '1' then
- if d_in.decode.mul_signed = '1' then
- v.m.data1 := (others => mul_a(31));
- v.m.data1(31 downto 0) := mul_a(31 downto 0);
- v.m.data2 := (others => mul_b(31));
- v.m.data2(31 downto 0) := mul_b(31 downto 0);
- else
- v.m.data1 := '0' & x"00000000" & mul_a(31 downto 0);
- v.m.data2 := '0' & x"00000000" & mul_b(31 downto 0);
- end if;
- else
- if d_in.decode.mul_signed = '1' then
- v.m.data1 := mul_a(63) & mul_a;
- v.m.data2 := mul_b(63) & mul_b;
- else
- v.m.data1 := '0' & mul_a;
- v.m.data2 := '0' & mul_b;
- end if;
- end if;
+ v.e.insn := d_in.insn;
+ v.e.data_len := length;
+ v.e.byte_reverse := d_in.decode.byte_reverse;
+ v.e.sign_extend := d_in.decode.sign_extend;
+ v.e.update := d_in.decode.update;
+ v.e.reserve := d_in.decode.reserve;
- -- load/store unit
- v.l.update_reg := decoded_reg_a.reg;
- v.l.addr1 := decoded_reg_a.data;
- v.l.addr2 := decoded_reg_b.data;
- v.l.data := decoded_reg_c.data;
- v.l.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
+ -- issue control
+ control_valid_in <= d_in.valid;
+ control_sgl_pipe <= d_in.decode.sgl_pipe;
- if d_in.decode.insn_type = OP_LOAD then
- v.l.load := '1';
- else
- v.l.load := '0';
- end if;
+ gpr_write_valid <= decoded_reg_o.reg_valid;
+ gpr_write <= decoded_reg_o.reg;
+ gpr_bypassable <= '0';
+ if EX1_BYPASS and d_in.decode.unit = ALU then
+ gpr_bypassable <= '1';
+ end if;
- case d_in.decode.length is
- when is1B =>
- v.l.length := "0001";
- when is2B =>
- v.l.length := "0010";
- when is4B =>
- v.l.length := "0100";
- when is8B =>
- v.l.length := "1000";
- when NONE =>
- v.l.length := "0000";
- end case;
+ gpr_a_read_valid <= decoded_reg_a.reg_valid;
+ gpr_a_read <= decoded_reg_a.reg;
- v.l.byte_reverse := d_in.decode.byte_reverse;
- v.l.sign_extend := d_in.decode.sign_extend;
- v.l.update := d_in.decode.update;
+ gpr_b_read_valid <= decoded_reg_b.reg_valid;
+ gpr_b_read <= decoded_reg_b.reg;
- -- single issue
+ gpr_c_read_valid <= decoded_reg_c.reg_valid;
+ gpr_c_read <= gspr_to_gpr(decoded_reg_c.reg);
- if complete_in = '1' then
- v_int.outstanding := v_int.outstanding - 1;
- end if;
-
- -- state machine to handle instructions that must be single
- -- through the pipeline.
- stall_out <= '0';
- is_valid := d_in.valid;
- case v_int.state is
- when IDLE =>
- if (flush_in = '0') and (d_in.valid = '1') and (d_in.decode.sgl_pipe = '1') then
- if v_int.outstanding /= 0 then
- v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
- stall_out <= '1';
- is_valid := '0';
- else
- -- send insn out and wait on it to complete
- v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
- end if;
- end if;
+ cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
- when WAIT_FOR_PREV_TO_COMPLETE =>
- if v_int.outstanding = 0 then
- -- send insn out and wait on it to complete
- v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
- else
- stall_out <= '1';
- is_valid := '0';
- end if;
-
- when WAIT_FOR_CURR_TO_COMPLETE =>
- if v_int.outstanding = 0 then
- v_int.state := IDLE;
- else
- stall_out <= '1';
- is_valid := '0';
- end if;
- end case;
-
- v.e.valid := '0';
- v.m.valid := '0';
- v.l.valid := '0';
- case d_in.decode.unit is
- when ALU =>
- v.e.valid := is_valid;
- when LDST =>
- v.l.valid := is_valid;
- when MUL =>
- v.m.valid := is_valid;
- when NONE =>
- v.e.valid := is_valid;
+ v.e.valid := control_valid_out;
+ if d_in.decode.unit = NONE then
v.e.insn_type := OP_ILLEGAL;
- end case;
-
- if flush_in = '1' then
- v.e.valid := '0';
- v.m.valid := '0';
- v.l.valid := '0';
- end if;
-
- -- track outstanding instructions
- if v.e.valid = '1' or v.l.valid = '1' or v.m.valid = '1' then
- v_int.outstanding := v_int.outstanding + 1;
end if;
if rst = '1' then
- v_int.state := IDLE;
- v_int.outstanding := 0;
v.e := Decode2ToExecute1Init;
- v.l := Decode2ToLoadStore1Init;
- v.m := Decode2ToMultiplyInit;
end if;
-- Update registers
rin <= v;
- rin_int <= v_int;
-- Update outputs
e_out <= r.e;
- l_out <= r.l;
- m_out <= r.m;
end process;
end architecture behaviour;
projects / microwatt.git / blobdiff