/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2001-2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#ifndef __ALPHA_CONSOLE_HH__
#define __ALPHA_CONSOLE_HH__
-#include "sim/host.hh"
+#include "base/range.hh"
#include "dev/alpha_access.h"
-#include "mem/functional_mem/mmap_device.hh"
-#include "dev/tsunami_io.hh"
+#include "dev/io_device.hh"
+#include "sim/host.hh"
+#include "sim/sim_object.hh"
class BaseCPU;
class SimConsole;
class System;
-class TlaserClock;
+class Platform;
class SimpleDisk;
/*
* primarily used doing boot before the kernel has loaded its device
* drivers.
*/
-class AlphaConsole : public MmapDevice
+class AlphaConsole : public PioDevice
{
protected:
union {
AlphaAccess *alphaAccess;
- uint8_t *consoleData;
+ uint8_t *consoleData;
};
/** the disk must be accessed from the console */
/** the system console (the terminal) is accessable from the console */
SimConsole *console;
+ Addr addr;
+ static const Addr size = 0x80; // equal to sizeof(alpha_access);
+
public:
/** Standard Constructor */
- AlphaConsole(const std::string &name, SimConsole *cons,
- SimpleDisk *d, int size,
- System *system, BaseCPU *cpu,
- TsunamiIO *clock, int num_cpus,
- Addr addr, Addr mask, MemoryController *mmu);
+ AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
+ System *system, BaseCPU *cpu, Platform *platform,
+ int num_cpus, MemoryController *mmu, Addr addr,
+ HierParams *hier, Bus *bus);
- public:
/**
* memory mapped reads and writes
*/
*/
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);
+
+ public:
+ Tick cacheAccess(MemReqPtr &req);
};
#endif // __ALPHA_CONSOLE_HH__