Better handling of latency/frequency parameter types

[gem5.git] / dev / alpha_console.hh

diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh
index e4aeb2417515e98c9cf66cc6e6c4828b2e438b7c..96b0a22c2a2e56a9e5197d5dd7943abc2dc68861 100644 (file)
--- a/dev/alpha_console.hh
+++ b/dev/alpha_console.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2001-2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -33,14 +33,15 @@
 #ifndef __ALPHA_CONSOLE_HH__
 #define __ALPHA_CONSOLE_HH__
 
-#include "sim/host.hh"
+#include "base/range.hh"
 #include "dev/alpha_access.h"
-#include "mem/functional_mem/mmap_device.hh"
+#include "dev/io_device.hh"
+#include "sim/host.hh"
+#include "sim/sim_object.hh"
 
 class BaseCPU;
 class SimConsole;
 class System;
-class TlaserClock;
 class SimpleDisk;
 
 /*
@@ -68,7 +69,7 @@ class SimpleDisk;
  * primarily used doing boot before the kernel has loaded its device
  * drivers.
  */
-class AlphaConsole : public MmapDevice
+class AlphaConsole : public PioDevice
 {
   protected:
     union {
@@ -82,26 +83,30 @@ class AlphaConsole : public MmapDevice
     /** the system console (the terminal) is accessable from the console */
     SimConsole *console;
 
+    Addr addr;
+    static const Addr size = 0x80; // equal to sizeof(alpha_access);
+
   public:
     /** Standard Constructor */
-    AlphaConsole(const std::string &name, SimConsole *cons,
-                 SimpleDisk *d, int size,
-                 System *system, BaseCPU *cpu,
-                 TlaserClock *clock, int num_cpus,
-                 Addr addr, Addr mask, MemoryController *mmu);
+    AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
+                 System *system, BaseCPU *cpu, Platform *platform,
+                 int num_cpus, MemoryController *mmu, Addr addr,
+                 HierParams *hier, Bus *bus);
 
-  public:
     /**
      * memory mapped reads and writes
      */
-    virtual Fault read(MemReqPtr req, uint8_t *data);
-    virtual Fault write(MemReqPtr req, const uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     /**
      * standard serialization routines for checkpointing
      */
     virtual void serialize(std::ostream &os);
-    virtual void unserialize(const IniFile *db, const std::string &section);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+  public:
+    Tick cacheAccess(MemReqPtr &req);
 };
 
 #endif // __ALPHA_CONSOLE_HH__