More documentation for 1.1 release.

[gem5.git] / dev / ide_ctrl.cc

diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index 6ad80e69d0eb00a341f3f2bf63f68816e06dc0c1..9aa3094abbb3f53869d68164de71f4d61b20f675 100644 (file)
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -92,7 +92,7 @@ IdeController::IdeController(Params *p)
 
     // create the PIO and DMA interfaces
     if (params()->host_bus) {
-        pioInterface = newPioInterface(name(), params()->hier,
+        pioInterface = newPioInterface(name() + ".pio", params()->hier,
                                        params()->host_bus, this,
                                        &IdeController::cacheAccess);
 
@@ -101,10 +101,13 @@ IdeController::IdeController(Params *p)
                                              params()->host_bus, 1,
                                              true);
         pioLatency = params()->pio_latency * params()->host_bus->clockRate;
+    } else {
+        pioInterface = NULL;
+        dmaInterface = NULL;
     }
 
     // setup the disks attached to controller
-    memset(disks, 0, sizeof(IdeDisk *) * 4);
+    memset(disks, 0, sizeof(disks));
     dev[0] = 0;
     dev[1] = 0;
 
@@ -299,8 +302,10 @@ IdeController::writeConfig(int offset, int size, const uint8_t *data)
         switch(size) {
           case sizeof(uint8_t):
             config_regs.data[config_offset] = *data;
+            break;
           case sizeof(uint16_t):
             *(uint16_t*)&config_regs.data[config_offset] = *(uint16_t*)data;
+            break;
           case sizeof(uint32_t):
             *(uint32_t*)&config_regs.data[config_offset] = *(uint32_t*)data;
             break;
@@ -484,8 +489,8 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
             // select the current disk based on DEV bit
             disk = getDisk(channel);
 
-            oldVal = letoh(bmi_regs.chan[channel].bmic);
-            newVal = letoh(*data);
+            oldVal = bmi_regs.chan[channel].bmic;
+            newVal = *data;
 
             // if a DMA transfer is in progress, R/W control cannot change
             if (oldVal & SSBM) {
@@ -501,8 +506,8 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
                     DPRINTF(IdeCtrl, "Stopping DMA transfer\n");
 
                     // clear the BMIDEA bit
-                    bmi_regs.chan[channel].bmis = letoh(
-                        letoh(bmi_regs.chan[channel].bmis) & ~BMIDEA);
+                    bmi_regs.chan[channel].bmis =
+                        bmi_regs.chan[channel].bmis & ~BMIDEA;
 
                     if (disks[disk] == NULL)
                         panic("DMA stop for disk %d which does not exist\n",
@@ -515,8 +520,8 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
                     DPRINTF(IdeCtrl, "Starting DMA transfer\n");
 
                     // set the BMIDEA bit
-                    bmi_regs.chan[channel].bmis = letoh(
-                        letoh(bmi_regs.chan[channel].bmis) | BMIDEA);
+                    bmi_regs.chan[channel].bmis =
+                        bmi_regs.chan[channel].bmis | BMIDEA;
 
                     if (disks[disk] == NULL)
                         panic("DMA start for disk %d which does not exist\n",
@@ -528,7 +533,7 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
             }
 
             // update the register value
-            bmi_regs.chan[channel].bmic = letoh(newVal);
+            bmi_regs.chan[channel].bmic = newVal;
             break;
 
             // Bus master IDE status register
@@ -537,8 +542,8 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
             if (req->size != sizeof(uint8_t))
                 panic("Invalid BMIS write size: %x\n", req->size);
 
-            oldVal = letoh(bmi_regs.chan[channel].bmis);
-            newVal = letoh(*data);
+            oldVal = bmi_regs.chan[channel].bmis;
+            newVal = *data;
 
             // the BMIDEA bit is RO
             newVal |= (oldVal & BMIDEA);
@@ -554,17 +559,20 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
             else
                 (oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE;
 
-            bmi_regs.chan[channel].bmis = letoh(newVal);
+            bmi_regs.chan[channel].bmis = newVal;
             break;
 
             // Bus master IDE descriptor table pointer register
           case BMIDTP0:
           case BMIDTP1:
-            if (req->size != sizeof(uint32_t))
-                panic("Invalid BMIDTP write size: %x\n", req->size);
+            {
+                if (req->size != sizeof(uint32_t))
+                    panic("Invalid BMIDTP write size: %x\n", req->size);
 
-            bmi_regs.chan[channel].bmidtp = letoh(
-                letoh(*(uint32_t*)data) & ~0x3);
+                uint32_t host_data =  letoh(*(uint32_t*)data);
+                host_data &= ~0x3;
+                bmi_regs.chan[channel].bmidtp = htole(host_data);
+            }
             break;
 
           default:
@@ -645,14 +653,17 @@ IdeController::serialize(std::ostream &os)
     SERIALIZE_SCALAR(bmi_size);
 
     // Serialize registers
-    SERIALIZE_ARRAY(bmi_regs.data, sizeof(bmi_regs));
-    SERIALIZE_ARRAY(dev, sizeof(dev));
-    SERIALIZE_ARRAY(config_regs.data, sizeof(config_regs));
+    SERIALIZE_ARRAY(bmi_regs.data,
+                    sizeof(bmi_regs.data) / sizeof(bmi_regs.data[0]));
+    SERIALIZE_ARRAY(dev, sizeof(dev) / sizeof(dev[0]));
+    SERIALIZE_ARRAY(config_regs.data,
+                    sizeof(config_regs.data) / sizeof(config_regs.data[0]));
 
     // Serialize internal state
     SERIALIZE_SCALAR(io_enabled);
     SERIALIZE_SCALAR(bm_enabled);
-    SERIALIZE_ARRAY(cmd_in_progress, sizeof(cmd_in_progress));
+    SERIALIZE_ARRAY(cmd_in_progress,
+                    sizeof(cmd_in_progress) / sizeof(cmd_in_progress[0]));
 }
 
 void
@@ -674,14 +685,17 @@ IdeController::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(bmi_size);
 
     // Unserialize registers
-    UNSERIALIZE_ARRAY(bmi_regs.data, sizeof(bmi_regs));
-    UNSERIALIZE_ARRAY(dev, sizeof(dev));
-    UNSERIALIZE_ARRAY(config_regs.data, sizeof(config_regs));
+    UNSERIALIZE_ARRAY(bmi_regs.data,
+                      sizeof(bmi_regs.data) / sizeof(bmi_regs.data[0]));
+    UNSERIALIZE_ARRAY(dev, sizeof(dev) / sizeof(dev[0]));
+    UNSERIALIZE_ARRAY(config_regs.data,
+                      sizeof(config_regs.data) / sizeof(config_regs.data[0]));
 
     // Unserialize internal state
     UNSERIALIZE_SCALAR(io_enabled);
     UNSERIALIZE_SCALAR(bm_enabled);
-    UNSERIALIZE_ARRAY(cmd_in_progress, sizeof(cmd_in_progress));
+    UNSERIALIZE_ARRAY(cmd_in_progress,
+                      sizeof(cmd_in_progress) / sizeof(cmd_in_progress[0]));
 
     if (pioInterface) {
         pioInterface->addAddrRange(RangeSize(pri_cmd_addr, pri_cmd_size));