Macros are nasty, so let's get rid of them. Convert all

[gem5.git] / dev / ide_ctrl.cc

diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index 46a0e817933c9917b1c83bbab4a173ea1188a841..aa0217745281ba41e7c29d13ad30f222060f9ac1 100644 (file)
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -34,16 +34,16 @@
 #include "base/trace.hh"
 #include "cpu/intr_control.hh"
 #include "dev/dma.hh"
-#include "dev/pcireg.h"
-#include "dev/pciconfigall.hh"
-#include "dev/ide_disk.hh"
 #include "dev/ide_ctrl.hh"
+#include "dev/ide_disk.hh"
+#include "dev/pciconfigall.hh"
+#include "dev/pcireg.h"
+#include "dev/platform.hh"
 #include "dev/tsunami_cchip.hh"
 #include "mem/bus/bus.hh"
+#include "mem/bus/dma_interface.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/bus/dma_interface.hh"
-#include "dev/tsunami.hh"
 #include "mem/functional_mem/memory_control.hh"
 #include "mem/functional_mem/physical_memory.hh"
 #include "sim/builder.hh"
@@ -60,12 +60,9 @@ IdeController::IdeController(const string &name, IntrControl *ic,
                              MemoryController *mmu, PciConfigAll *cf,
                              PciConfigData *cd, Tsunami *t, uint32_t bus_num,
                              uint32_t dev_num, uint32_t func_num,
-                             Bus *host_bus, HierParams *hier)
+                             Bus *host_bus, Tick pio_latency, HierParams *hier)
     : PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
 {
-    // put back pointer into Tsunami
-    tsunami->disk_controller = this;
-
     // initialize the PIO interface addresses
     pri_cmd_addr = 0;
     pri_cmd_size = BARSize[0];
@@ -105,6 +102,7 @@ IdeController::IdeController(const string &name, IntrControl *ic,
 
         dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus,
                                              host_bus, 1);
+        pioLatency = pio_latency * host_bus->clockRatio;
     }
 
     // setup the disks attached to controller
@@ -192,6 +190,22 @@ IdeController::getDisk(IdeDisk *diskPtr)
     return -1;
 }
 
+bool
+IdeController::isDiskSelected(IdeDisk *diskPtr)
+{
+    for (int i = 0; i < 4; i++) {
+        if ((long)diskPtr == (long)disks[i]) {
+            // is disk is on primary or secondary channel
+            int channel = i/2;
+            // is disk the master or slave
+            int devID = i%2;
+
+            return (dev[channel] == devID);
+        }
+    }
+    panic("Unable to find disk by pointer!!\n");
+}
+
 ////
 // Command completion
 ////
@@ -228,13 +242,13 @@ IdeController::setDmaComplete(IdeDisk *disk)
 void
 IdeController::intrPost()
 {
-    tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
+    tsunami->postPciInt(configData->config.hdr.pci0.interruptLine);
 }
 
 void
 IdeController::intrClear()
 {
-    tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
+    tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine);
 }
 
 ////
@@ -245,7 +259,7 @@ Tick
 IdeController::cacheAccess(MemReqPtr &req)
 {
     // @todo Add more accurate timing to cache access
-    return curTick + 1000;
+    return curTick + pioLatency;
 }
 
 ////
@@ -360,10 +374,10 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
         if (BARAddrs[0] != 0) {
             pri_cmd_addr = BARAddrs[0];
             if (pioInterface)
-                pioInterface->addAddrRange(pri_cmd_addr,
-                                           pri_cmd_addr + pri_cmd_size - 1);
+                pioInterface->addAddrRange(RangeSize(pri_cmd_addr,
+                                                     pri_cmd_size));
 
-            pri_cmd_addr &= PA_UNCACHED_MASK;
+            pri_cmd_addr &= EV5::PAddrUncachedMask;
         }
         break;
 
@@ -371,10 +385,10 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
         if (BARAddrs[1] != 0) {
             pri_ctrl_addr = BARAddrs[1];
             if (pioInterface)
-                pioInterface->addAddrRange(pri_ctrl_addr,
-                                           pri_ctrl_addr + pri_ctrl_size - 1);
+                pioInterface->addAddrRange(RangeSize(pri_ctrl_addr,
+                                                     pri_ctrl_size));
 
-            pri_ctrl_addr &= PA_UNCACHED_MASK;
+            pri_ctrl_addr &= EV5::PAddrUncachedMask;
         }
         break;
 
@@ -382,10 +396,10 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
         if (BARAddrs[2] != 0) {
             sec_cmd_addr = BARAddrs[2];
             if (pioInterface)
-                pioInterface->addAddrRange(sec_cmd_addr,
-                                           sec_cmd_addr + sec_cmd_size - 1);
+                pioInterface->addAddrRange(RangeSize(sec_cmd_addr,
+                                                     sec_cmd_size));
 
-            sec_cmd_addr &= PA_UNCACHED_MASK;
+            sec_cmd_addr &= EV5::PAddrUncachedMask;
         }
         break;
 
@@ -393,10 +407,10 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
         if (BARAddrs[3] != 0) {
             sec_ctrl_addr = BARAddrs[3];
             if (pioInterface)
-                pioInterface->addAddrRange(sec_ctrl_addr,
-                                           sec_ctrl_addr + sec_ctrl_size - 1);
+                pioInterface->addAddrRange(RangeSize(sec_ctrl_addr,
+                                                     sec_ctrl_size));
 
-            sec_ctrl_addr &= PA_UNCACHED_MASK;
+            sec_ctrl_addr &= EV5::PAddrUncachedMask;
         }
         break;
 
@@ -404,9 +418,9 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
         if (BARAddrs[4] != 0) {
             bmi_addr = BARAddrs[4];
             if (pioInterface)
-                pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
+                pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size));
 
-            bmi_addr &= PA_UNCACHED_MASK;
+            bmi_addr &= EV5::PAddrUncachedMask;
         }
         break;
     }
@@ -658,15 +672,11 @@ IdeController::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_ARRAY(cmd_in_progress, 4);
 
     if (pioInterface) {
-        pioInterface->addAddrRange(pri_cmd_addr, pri_cmd_addr +
-                                   pri_cmd_size - 1);
-        pioInterface->addAddrRange(pri_ctrl_addr, pri_ctrl_addr +
-                                   pri_ctrl_size - 1);
-        pioInterface->addAddrRange(sec_cmd_addr, sec_cmd_addr +
-                                   sec_cmd_size - 1);
-        pioInterface->addAddrRange(sec_ctrl_addr, sec_ctrl_addr +
-                                   sec_ctrl_size - 1);
-        pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
+        pioInterface->addAddrRange(RangeSize(pri_cmd_addr, pri_cmd_size));
+        pioInterface->addAddrRange(RangeSize(pri_ctrl_addr, pri_ctrl_size));
+        pioInterface->addAddrRange(RangeSize(sec_cmd_addr, sec_cmd_size));
+        pioInterface->addAddrRange(RangeSize(sec_ctrl_addr, sec_ctrl_size));
+        pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size));
    }
 }
 
@@ -684,6 +694,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
     Param<uint32_t> pci_dev;
     Param<uint32_t> pci_func;
     SimObjectParam<Bus *> io_bus;
+    Param<Tick> pio_latency;
     SimObjectParam<HierParams *> hier;
 
 END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
@@ -700,6 +711,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
     INIT_PARAM(pci_dev, "PCI device number"),
     INIT_PARAM(pci_func, "PCI function code"),
     INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
 END_INIT_SIM_OBJECT_PARAMS(IdeController)
@@ -708,7 +720,7 @@ CREATE_SIM_OBJECT(IdeController)
 {
     return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
                              configspace, configdata, tsunami, pci_bus,
-                             pci_dev, pci_func, io_bus, hier);
+                             pci_dev, pci_func, io_bus, pio_latency, hier);
 }
 
 REGISTER_SIM_OBJECT("IdeController", IdeController)