#include "base/trace.hh"
#include "cpu/intr_control.hh"
#include "dev/dma.hh"
-#include "dev/pcireg.h"
-#include "dev/pciconfigall.hh"
-#include "dev/ide_disk.hh"
#include "dev/ide_ctrl.hh"
+#include "dev/ide_disk.hh"
+#include "dev/pciconfigall.hh"
+#include "dev/pcireg.h"
+#include "dev/platform.hh"
#include "dev/tsunami_cchip.hh"
#include "mem/bus/bus.hh"
+#include "mem/bus/dma_interface.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
-#include "mem/bus/dma_interface.hh"
-#include "dev/tsunami.hh"
#include "mem/functional_mem/memory_control.hh"
#include "mem/functional_mem/physical_memory.hh"
#include "sim/builder.hh"
Bus *host_bus, Tick pio_latency, HierParams *hier)
: PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
{
- // put back pointer into Tsunami
- tsunami->disk_controller = this;
-
// initialize the PIO interface addresses
pri_cmd_addr = 0;
pri_cmd_size = BARSize[0];
void
IdeController::intrPost()
{
- tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
+ tsunami->postPciInt(configData->config.hdr.pci0.interruptLine);
}
void
IdeController::intrClear()
{
- tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
+ tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine);
}
////
if (BARAddrs[0] != 0) {
pri_cmd_addr = BARAddrs[0];
if (pioInterface)
- pioInterface->addAddrRange(pri_cmd_addr,
- pri_cmd_addr + pri_cmd_size - 1);
+ pioInterface->addAddrRange(RangeSize(pri_cmd_addr,
+ pri_cmd_size));
- pri_cmd_addr &= PA_UNCACHED_MASK;
+ pri_cmd_addr &= EV5::PAddrUncachedMask;
}
break;
if (BARAddrs[1] != 0) {
pri_ctrl_addr = BARAddrs[1];
if (pioInterface)
- pioInterface->addAddrRange(pri_ctrl_addr,
- pri_ctrl_addr + pri_ctrl_size - 1);
+ pioInterface->addAddrRange(RangeSize(pri_ctrl_addr,
+ pri_ctrl_size));
- pri_ctrl_addr &= PA_UNCACHED_MASK;
+ pri_ctrl_addr &= EV5::PAddrUncachedMask;
}
break;
if (BARAddrs[2] != 0) {
sec_cmd_addr = BARAddrs[2];
if (pioInterface)
- pioInterface->addAddrRange(sec_cmd_addr,
- sec_cmd_addr + sec_cmd_size - 1);
+ pioInterface->addAddrRange(RangeSize(sec_cmd_addr,
+ sec_cmd_size));
- sec_cmd_addr &= PA_UNCACHED_MASK;
+ sec_cmd_addr &= EV5::PAddrUncachedMask;
}
break;
if (BARAddrs[3] != 0) {
sec_ctrl_addr = BARAddrs[3];
if (pioInterface)
- pioInterface->addAddrRange(sec_ctrl_addr,
- sec_ctrl_addr + sec_ctrl_size - 1);
+ pioInterface->addAddrRange(RangeSize(sec_ctrl_addr,
+ sec_ctrl_size));
- sec_ctrl_addr &= PA_UNCACHED_MASK;
+ sec_ctrl_addr &= EV5::PAddrUncachedMask;
}
break;
if (BARAddrs[4] != 0) {
bmi_addr = BARAddrs[4];
if (pioInterface)
- pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
+ pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size));
- bmi_addr &= PA_UNCACHED_MASK;
+ bmi_addr &= EV5::PAddrUncachedMask;
}
break;
}
UNSERIALIZE_ARRAY(cmd_in_progress, 4);
if (pioInterface) {
- pioInterface->addAddrRange(pri_cmd_addr, pri_cmd_addr +
- pri_cmd_size - 1);
- pioInterface->addAddrRange(pri_ctrl_addr, pri_ctrl_addr +
- pri_ctrl_size - 1);
- pioInterface->addAddrRange(sec_cmd_addr, sec_cmd_addr +
- sec_cmd_size - 1);
- pioInterface->addAddrRange(sec_ctrl_addr, sec_ctrl_addr +
- sec_ctrl_size - 1);
- pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
+ pioInterface->addAddrRange(RangeSize(pri_cmd_addr, pri_cmd_size));
+ pioInterface->addAddrRange(RangeSize(pri_ctrl_addr, pri_ctrl_size));
+ pioInterface->addAddrRange(RangeSize(sec_cmd_addr, sec_cmd_size));
+ pioInterface->addAddrRange(RangeSize(sec_ctrl_addr, sec_ctrl_size));
+ pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size));
}
}