/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include "base/trace.hh"
#include "cpu/intr_control.hh"
#include "dev/dma.hh"
-#include "dev/pcireg.h"
-#include "dev/pciconfigall.hh"
-#include "dev/ide_disk.hh"
#include "dev/ide_ctrl.hh"
+#include "dev/ide_disk.hh"
+#include "dev/pciconfigall.hh"
+#include "dev/pcireg.h"
+#include "dev/platform.hh"
#include "dev/tsunami_cchip.hh"
#include "mem/bus/bus.hh"
+#include "mem/bus/dma_interface.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
-#include "mem/bus/dma_interface.hh"
-#include "dev/tsunami.hh"
#include "mem/functional_mem/memory_control.hh"
#include "mem/functional_mem/physical_memory.hh"
#include "sim/builder.hh"
MemoryController *mmu, PciConfigAll *cf,
PciConfigData *cd, Tsunami *t, uint32_t bus_num,
uint32_t dev_num, uint32_t func_num,
- Bus *host_bus, HierParams *hier)
+ Bus *host_bus, Tick pio_latency, HierParams *hier)
: PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
{
- // put back pointer into Tsunami
- tsunami->disk_controller = this;
-
// initialize the PIO interface addresses
pri_cmd_addr = 0;
pri_cmd_size = BARSize[0];
dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus,
host_bus, 1);
+ pioLatency = pio_latency * host_bus->clockRatio;
}
// setup the disks attached to controller
return -1;
}
+bool
+IdeController::isDiskSelected(IdeDisk *diskPtr)
+{
+ for (int i = 0; i < 4; i++) {
+ if ((long)diskPtr == (long)disks[i]) {
+ // is disk is on primary or secondary channel
+ int channel = i/2;
+ // is disk the master or slave
+ int devID = i%2;
+
+ return (dev[channel] == devID);
+ }
+ }
+ panic("Unable to find disk by pointer!!\n");
+}
+
////
// Command completion
////
void
IdeController::intrPost()
{
- tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
+ tsunami->postPciInt(configData->config.hdr.pci0.interruptLine);
}
void
IdeController::intrClear()
{
- tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
+ tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine);
}
////
IdeController::cacheAccess(MemReqPtr &req)
{
// @todo Add more accurate timing to cache access
- return curTick + 1000;
+ return curTick + pioLatency;
}
////
void
IdeController::ReadConfig(int offset, int size, uint8_t *data)
{
+
+#if TRACING_ON
Addr origOffset = offset;
+#endif
if (offset < PCI_DEVICE_SPECIFIC) {
PciDev::ReadConfig(offset, size, data);
memcpy((void *)&pci_regs[offset], (void *)&data, size);
}
- if (offset == PCI_COMMAND) {
- if (config.data[offset] & IOSE)
+ // Catch the writes to specific PCI registers that have side affects
+ // (like updating the PIO ranges)
+ switch (offset) {
+ case PCI_COMMAND:
+ if (config.data[offset] & PCI_CMD_IOSE)
io_enabled = true;
else
io_enabled = false;
- if (config.data[offset] & BME)
+ if (config.data[offset] & PCI_CMD_BME)
bm_enabled = true;
else
bm_enabled = false;
+ break;
- } else if (data != 0xffffffff) {
- switch (offset) {
- case PCI0_BASE_ADDR0:
+ case PCI0_BASE_ADDR0:
+ if (BARAddrs[0] != 0) {
pri_cmd_addr = BARAddrs[0];
if (pioInterface)
- pioInterface->addAddrRange(pri_cmd_addr,
- pri_cmd_addr + pri_cmd_size - 1);
+ pioInterface->addAddrRange(RangeSize(pri_cmd_addr,
+ pri_cmd_size));
- pri_cmd_addr = pri_cmd_addr & PA_UNCACHED_MASK;
- break;
+ pri_cmd_addr &= EV5::PAddrUncachedMask;
+ }
+ break;
- case PCI0_BASE_ADDR1:
+ case PCI0_BASE_ADDR1:
+ if (BARAddrs[1] != 0) {
pri_ctrl_addr = BARAddrs[1];
if (pioInterface)
- pioInterface->addAddrRange(pri_ctrl_addr,
- pri_ctrl_addr + pri_ctrl_size - 1);
+ pioInterface->addAddrRange(RangeSize(pri_ctrl_addr,
+ pri_ctrl_size));
- pri_ctrl_addr = pri_ctrl_addr & PA_UNCACHED_MASK;
- break;
+ pri_ctrl_addr &= EV5::PAddrUncachedMask;
+ }
+ break;
- case PCI0_BASE_ADDR2:
+ case PCI0_BASE_ADDR2:
+ if (BARAddrs[2] != 0) {
sec_cmd_addr = BARAddrs[2];
if (pioInterface)
- pioInterface->addAddrRange(sec_cmd_addr,
- sec_cmd_addr + sec_cmd_size - 1);
+ pioInterface->addAddrRange(RangeSize(sec_cmd_addr,
+ sec_cmd_size));
- sec_cmd_addr = sec_cmd_addr & PA_UNCACHED_MASK;
- break;
+ sec_cmd_addr &= EV5::PAddrUncachedMask;
+ }
+ break;
- case PCI0_BASE_ADDR3:
+ case PCI0_BASE_ADDR3:
+ if (BARAddrs[3] != 0) {
sec_ctrl_addr = BARAddrs[3];
if (pioInterface)
- pioInterface->addAddrRange(sec_ctrl_addr,
- sec_ctrl_addr + sec_ctrl_size - 1);
+ pioInterface->addAddrRange(RangeSize(sec_ctrl_addr,
+ sec_ctrl_size));
- sec_ctrl_addr = sec_ctrl_addr & PA_UNCACHED_MASK;
- break;
+ sec_ctrl_addr &= EV5::PAddrUncachedMask;
+ }
+ break;
- case PCI0_BASE_ADDR4:
+ case PCI0_BASE_ADDR4:
+ if (BARAddrs[4] != 0) {
bmi_addr = BARAddrs[4];
if (pioInterface)
- pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
+ pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size));
- bmi_addr = bmi_addr & PA_UNCACHED_MASK;
- break;
+ bmi_addr &= EV5::PAddrUncachedMask;
}
+ break;
}
}
void
IdeController::serialize(std::ostream &os)
{
+ // Serialize the PciDev base class
+ PciDev::serialize(os);
+
// Serialize register addresses and sizes
SERIALIZE_SCALAR(pri_cmd_addr);
SERIALIZE_SCALAR(pri_cmd_size);
void
IdeController::unserialize(Checkpoint *cp, const std::string §ion)
{
+ // Unserialize the PciDev base class
+ PciDev::unserialize(cp, section);
+
// Unserialize register addresses and sizes
UNSERIALIZE_SCALAR(pri_cmd_addr);
UNSERIALIZE_SCALAR(pri_cmd_size);
UNSERIALIZE_SCALAR(io_enabled);
UNSERIALIZE_SCALAR(bm_enabled);
UNSERIALIZE_ARRAY(cmd_in_progress, 4);
+
+ if (pioInterface) {
+ pioInterface->addAddrRange(RangeSize(pri_cmd_addr, pri_cmd_size));
+ pioInterface->addAddrRange(RangeSize(pri_ctrl_addr, pri_ctrl_size));
+ pioInterface->addAddrRange(RangeSize(sec_cmd_addr, sec_cmd_size));
+ pioInterface->addAddrRange(RangeSize(sec_ctrl_addr, sec_ctrl_size));
+ pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size));
+ }
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
Param<uint32_t> pci_bus;
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
- SimObjectParam<Bus *> host_bus;
+ SimObjectParam<Bus *> io_bus;
+ Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
INIT_PARAM(pci_bus, "PCI bus ID"),
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
- INIT_PARAM_DFLT(host_bus, "Host bus to attach to", NULL),
+ INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL),
+ INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
END_INIT_SIM_OBJECT_PARAMS(IdeController)
{
return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
configspace, configdata, tsunami, pci_bus,
- pci_dev, pci_func, host_bus, hier);
+ pci_dev, pci_func, io_bus, pio_latency, hier);
}
REGISTER_SIM_OBJECT("IdeController", IdeController)
projects / gem5.git / blobdiff