#define UDMACTL (5)
#define UDMATIM (6)
-// PCI Command bit fields
-#define BME 0x04 // Bus master function enable
-#define IOSE 0x01 // I/O space enable
-
typedef enum RegType {
COMMAND_BLOCK = 0,
CONTROL_BLOCK,
/** Select the disk based on a pointer */
int getDisk(IdeDisk *diskPtr);
+ public:
+ /** See if a disk is selected based on its pointer */
+ bool isDiskSelected(IdeDisk *diskPtr);
+
public:
/**
* Constructs and initializes this controller.
MemoryController *mmu, PciConfigAll *cf,
PciConfigData *cd, Tsunami *t,
uint32_t bus_num, uint32_t dev_num, uint32_t func_num,
- Bus *host_bus, HierParams *hier);
+ Bus *host_bus, Tick pio_latency, HierParams *hier);
/**
* Deletes the connected devices.
*/
virtual Fault write(MemReqPtr &req, const uint8_t *data);
- /**
- * Cache access timing specific to device
- * @param req Memory request
- */
- Tick cacheAccess(MemReqPtr &req);
-
/**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
*/
virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ /**
+ * Return how long this access will take.
+ * @param req the memory request to calcuate
+ * @return Tick when the request is done
+ */
+ Tick cacheAccess(MemReqPtr &req);
};
#endif // __IDE_CTRL_HH_