sort #includes

[gem5.git] / dev / ide_ctrl.hh

diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh
index b4de9703602802d061053a7be66d8e102af37e33..b29e5ae9a1d3bc797b18e3f374d287ff07321670 100644 (file)
--- a/dev/ide_ctrl.hh
+++ b/dev/ide_ctrl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,7 +27,8 @@
  */
 
 /** @file
- * Simple PCI IDE controller with bus mastering capability
+ * Simple PCI IDE controller with bus mastering capability and UDMA
+ * modeled after controller in the Intel PIIX4 chip
  */
 
 #ifndef __IDE_CTRL_HH__
@@ -73,10 +74,6 @@
 #define UDMACTL (5)
 #define UDMATIM (6)
 
-// PCI Command bit fields
-#define BME     0x04 // Bus master function enable
-#define IOSE    0x01 // I/O space enable
-
 typedef enum RegType {
     COMMAND_BLOCK = 0,
     CONTROL_BLOCK,
@@ -139,65 +136,17 @@ class IdeController : public PciDev
   private:
     /** Parse the access address to pass on to device */
     void parseAddr(const Addr &addr, Addr &offset, bool &primary,
-                   RegType_t &type)
-    {
-        offset = addr;
-
-        if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
-            offset -= pri_cmd_addr;
-            type = COMMAND_BLOCK;
-            primary = true;
-        } else if (addr >= pri_ctrl_addr &&
-                   addr < (pri_ctrl_addr + pri_ctrl_size)) {
-            offset -= pri_ctrl_addr;
-            type = CONTROL_BLOCK;
-            primary = true;
-        } else if (addr >= sec_cmd_addr &&
-                   addr < (sec_cmd_addr + sec_cmd_size)) {
-            offset -= sec_cmd_addr;
-            type = COMMAND_BLOCK;
-            primary = false;
-        } else if (addr >= sec_ctrl_addr &&
-                   addr < (sec_ctrl_addr + sec_ctrl_size)) {
-            offset -= sec_ctrl_addr;
-            type = CONTROL_BLOCK;
-            primary = false;
-        } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
-            offset -= bmi_addr;
-            type = BMI_BLOCK;
-            primary = (offset < BMIC1) ? true : false;
-        } else {
-            panic("IDE controller access to invalid address: %#x\n", addr);
-        }
-    };
+                   RegType_t &type);
 
     /** Select the disk based on the channel and device bit */
-    int getDisk(bool primary)
-    {
-        int disk = 0;
-        uint8_t *devBit = &dev[0];
-
-        if (!primary) {
-            disk += 2;
-            devBit = &dev[1];
-        }
-
-        disk += *devBit;
-
-        assert(*devBit == 0 || *devBit == 1);
-
-        return disk;
-    };
+    int getDisk(bool primary);
 
     /** Select the disk based on a pointer */
-    int getDisk(IdeDisk *diskPtr)
-    {
-        for (int i = 0; i < 4; i++) {
-            if ((long)diskPtr == (long)disks[i])
-                return i;
-        }
-        return -1;
-    }
+    int getDisk(IdeDisk *diskPtr);
+
+  public:
+    /** See if a disk is selected based on its pointer */
+    bool isDiskSelected(IdeDisk *diskPtr);
 
   public:
     /**
@@ -218,7 +167,7 @@ class IdeController : public PciDev
                   MemoryController *mmu, PciConfigAll *cf,
                   PciConfigData *cd, Tsunami *t,
                   uint32_t bus_num, uint32_t dev_num, uint32_t func_num,
-                  Bus *host_bus, HierParams *hier);
+                  Bus *host_bus, Tick pio_latency, HierParams *hier);
 
     /**
      * Deletes the connected devices.
@@ -249,12 +198,6 @@ class IdeController : public PciDev
      */
     virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
-    /**
-     * Cache access timing specific to device
-     * @param req Memory request
-     */
-    Tick cacheAccess(MemReqPtr &req);
-
     /**
      * Serialize this object to the given output stream.
      * @param os The stream to serialize to.
@@ -268,5 +211,11 @@ class IdeController : public PciDev
      */
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
+    /**
+     * Return how long this access will take.
+     * @param req the memory request to calcuate
+     * @return Tick when the request is done
+     */
+    Tick cacheAccess(MemReqPtr &req);
 };
 #endif // __IDE_CTRL_HH_