/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*/
/** @file
- * Simple PCI IDE controller with bus mastering capability
+ * Simple PCI IDE controller with bus mastering capability and UDMA
+ * modeled after controller in the Intel PIIX4 chip
*/
#ifndef __IDE_CTRL_HH__
#define UDMACTL (5)
#define UDMATIM (6)
-// PCI Command bit fields
-#define BME 0x04 // Bus master function enable
-#define IOSE 0x01 // I/O space enable
-
typedef enum RegType {
COMMAND_BLOCK = 0,
CONTROL_BLOCK,
BMI_BLOCK
} RegType_t;
+class BaseInterface;
+class Bus;
+class HierParams;
class IdeDisk;
class IntrControl;
class PciConfigAll;
-class Tsunami;
class PhysicalMemory;
-class BaseInterface;
-class HierParams;
-class Bus;
+class Platform;
/**
* Device model for an Intel PIIX4 IDE controller
class IdeController : public PciDev
{
+ friend class IdeDisk;
+
private:
/** Primary command block registers */
Addr pri_cmd_addr;
bool bm_enabled;
bool cmd_in_progress[4];
- public:
- /** Pointer to the chipset */
- Tsunami *tsunami;
-
private:
/** IDE disks connected to controller */
IdeDisk *disks[4];
private:
/** Parse the access address to pass on to device */
void parseAddr(const Addr &addr, Addr &offset, bool &primary,
- RegType_t &type)
- {
- offset = addr;
-
- if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
- offset -= pri_cmd_addr;
- type = COMMAND_BLOCK;
- primary = true;
- } else if (addr >= pri_ctrl_addr &&
- addr < (pri_ctrl_addr + pri_ctrl_size)) {
- offset -= pri_ctrl_addr;
- type = CONTROL_BLOCK;
- primary = true;
- } else if (addr >= sec_cmd_addr &&
- addr < (sec_cmd_addr + sec_cmd_size)) {
- offset -= sec_cmd_addr;
- type = COMMAND_BLOCK;
- primary = false;
- } else if (addr >= sec_ctrl_addr &&
- addr < (sec_ctrl_addr + sec_ctrl_size)) {
- offset -= sec_ctrl_addr;
- type = CONTROL_BLOCK;
- primary = false;
- } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
- offset -= bmi_addr;
- type = BMI_BLOCK;
- primary = (offset < BMIC1) ? true : false;
- } else {
- panic("IDE controller access to invalid address: %#x\n", addr);
- }
- };
+ RegType_t &type);
/** Select the disk based on the channel and device bit */
- int getDisk(bool primary)
- {
- int disk = 0;
- uint8_t *devBit = &dev[0];
+ int getDisk(bool primary);
- if (!primary) {
- disk += 2;
- devBit = &dev[1];
- }
-
- disk += *devBit;
-
- assert(*devBit == 0 || *devBit == 1);
+ /** Select the disk based on a pointer */
+ int getDisk(IdeDisk *diskPtr);
- return disk;
- };
+ public:
+ /** See if a disk is selected based on its pointer */
+ bool isDiskSelected(IdeDisk *diskPtr);
- /** Select the disk based on a pointer */
- int getDisk(IdeDisk *diskPtr)
+ public:
+ struct Params : public PciDev::Params
{
- for (int i = 0; i < 4; i++) {
- if ((long)diskPtr == (long)disks[i])
- return i;
- }
- return -1;
- }
+ /** Array of disk objects */
+ std::vector<IdeDisk *> disks;
+ Bus *host_bus;
+ Tick pio_latency;
+ HierParams *hier;
+ };
+ const Params *params() const { return (const Params *)_params; }
public:
- /**
- * Constructs and initializes this controller.
- * @param name The name of this controller.
- * @param ic The interrupt controller.
- * @param mmu The memory controller
- * @param cf PCI config space
- * @param cd PCI config data
- * @param bus_num The PCI bus number
- * @param dev_num The PCI device number
- * @param func_num The PCI function number
- * @param host_bus The host bus to connect to
- * @param hier The hierarchy parameters
- */
- IdeController(const std::string &name, IntrControl *ic,
- const std::vector<IdeDisk *> &new_disks,
- MemoryController *mmu, PciConfigAll *cf,
- PciConfigData *cd, Tsunami *t,
- uint32_t bus_num, uint32_t dev_num, uint32_t func_num,
- Bus *host_bus, HierParams *hier);
-
- /**
- * Deletes the connected devices.
- */
+ IdeController(Params *p);
~IdeController();
virtual void WriteConfig(int offset, int size, uint32_t data);
virtual void ReadConfig(int offset, int size, uint8_t *data);
- void intrPost();
- void intrClear();
-
void setDmaComplete(IdeDisk *disk);
/**
*/
virtual Fault write(MemReqPtr &req, const uint8_t *data);
- /**
- * Cache access timing specific to device
- * @param req Memory request
- */
- Tick cacheAccess(MemReqPtr &req);
-
/**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
*/
virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ /**
+ * Return how long this access will take.
+ * @param req the memory request to calcuate
+ * @return Tick when the request is done
+ */
+ Tick cacheAccess(MemReqPtr &req);
};
#endif // __IDE_CTRL_HH_
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