/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
dmaWriteWaitEvent(this), dmaPrdReadEvent(this),
dmaReadEvent(this), dmaWriteEvent(this)
{
+ // Reset the device state
+ reset(id);
+
// calculate disk delay in microseconds
diskDelay = (delay * ticksPerSecond / 100000);
- // initialize the data buffer and shadow registers
- dataBuffer = new uint8_t[MAX_DMA_SIZE];
-
- memset(dataBuffer, 0, MAX_DMA_SIZE);
- memset(&cmdReg, 0, sizeof(CommandReg_t));
- memset(&curPrd.entry, 0, sizeof(PrdEntry_t));
-
- dmaInterfaceBytes = 0;
- curPrdAddr = 0;
- curSector = 0;
- curCommand = 0;
- cmdBytesLeft = 0;
- drqBytesLeft = 0;
- dmaRead = false;
- intrPending = false;
-
// fill out the drive ID structure
memset(&driveID, 0, sizeof(struct hd_driveid));
driveID.dma_ultra = 0x10;
// Statically set hardware config word
driveID.hw_config = 0x4001;
+}
+
+IdeDisk::~IdeDisk()
+{
+ // destroy the data buffer
+ delete [] dataBuffer;
+}
+
+void
+IdeDisk::reset(int id)
+{
+ // initialize the data buffer and shadow registers
+ dataBuffer = new uint8_t[MAX_DMA_SIZE];
+
+ memset(dataBuffer, 0, MAX_DMA_SIZE);
+ memset(&cmdReg, 0, sizeof(CommandReg_t));
+ memset(&curPrd.entry, 0, sizeof(PrdEntry_t));
+
+ dmaInterfaceBytes = 0;
+ curPrdAddr = 0;
+ curSector = 0;
+ cmdBytes = 0;
+ cmdBytesLeft = 0;
+ drqBytesLeft = 0;
+ dmaRead = false;
+ intrPending = false;
// set the device state to idle
dmaState = Dma_Idle;
}
// set the device ready bit
- cmdReg.status |= STATUS_DRDY_BIT;
-}
-
-IdeDisk::~IdeDisk()
-{
- // destroy the data buffer
- delete [] dataBuffer;
+ status = STATUS_DRDY_BIT;
}
////
// Utility functions
////
+bool
+IdeDisk::isDEVSelect()
+{
+ return ctrl->isDiskSelected(this);
+}
+
Addr
IdeDisk::pciToDma(Addr pciAddr)
{
// determine if an action needs to be taken on the state machine
if (offset == STATUS_OFFSET) {
action = ACT_STAT_READ;
+ *data = status; // status is in a shadow, explicity copy
} else if (offset == DATA_OFFSET) {
if (byte)
action = ACT_DATA_READ_BYTE;
if (!byte)
panic("Invalid 16-bit read from control block\n");
- *data = ((uint8_t *)&cmdReg)[STATUS_OFFSET];
+ *data = status;
}
if (action != ACT_NONE)
action = ACT_DATA_WRITE_BYTE;
else
action = ACT_DATA_WRITE_SHORT;
+ } else if (offset == SELECT_OFFSET) {
+ action = ACT_SELECT_WRITE;
}
} else {
if (!byte)
panic("Invalid 16-bit write to control block\n");
- if (*data & CONTROL_RST_BIT)
- panic("Software reset not supported!\n");
+ if (*data & CONTROL_RST_BIT) {
+ // force the device into the reset state
+ devState = Device_Srst;
+ action = ACT_SRST_SET;
+ } else if (devState == Device_Srst && !(*data & CONTROL_RST_BIT)) {
+ action = ACT_SRST_CLEAR;
+ }
nIENBit = (*data & CONTROL_IEN_BIT) ? true : false;
}
physmem->dma_addr(curPrdAddr, sizeof(PrdEntry_t)),
sizeof(PrdEntry_t));
- curPrdAddr += sizeof(PrdEntry_t);
+ DPRINTF(IdeDisk, "PRD: baseAddr:%#x (%#x) byteCount:%d (%d) eot:%#x sector:%d\n",
+ curPrd.getBaseAddr(), pciToDma(curPrd.getBaseAddr()),
+ curPrd.getByteCount(), (cmdBytesLeft/SectorSize),
+ curPrd.getEOT(), curSector);
+
+ // the prd pointer has already been translated, so just do an increment
+ curPrdAddr = curPrdAddr + sizeof(PrdEntry_t);
if (dmaRead)
doDmaRead();
writeDisk(curSector++, (uint8_t *)(dataBuffer + bytesWritten));
}
-#if 0
- // actually copy the data from memory to data buffer
- Addr dmaAddr =
- ctrl->tsunami->pchip->translatePciToDma(curPrd.getBaseAddr());
- memcpy((void *)dataBuffer,
- physmem->dma_addr(dmaAddr, curPrd.getByteCount()),
- curPrd.getByteCount());
-
- uint32_t bytesWritten = 0;
-
- while (bytesWritten < curPrd.getByteCount()) {
- if (cmdBytesLeft <= 0)
- panic("DMA data is larger than # sectors specified\n");
-
- writeDisk(curSector++, (uint8_t *)(dataBuffer + bytesWritten));
-
- bytesWritten += SectorSize;
- cmdBytesLeft -= SectorSize;
- }
-#endif
-
// check for the EOT
- if (curPrd.getEOT()){
+ if (curPrd.getEOT()) {
assert(cmdBytesLeft == 0);
dmaState = Dma_Idle;
updateState(ACT_DMA_DONE);
bytesInPage);
}
-#if 0
- Addr dmaAddr = ctrl->tsunami->pchip->
- translatePciToDma(curPrd.getBaseAddr());
-
- memcpy(physmem->dma_addr(dmaAddr, curPrd.getByteCount()),
- (void *)dataBuffer, curPrd.getByteCount());
-#endif
-
// check for the EOT
if (curPrd.getEOT()) {
assert(cmdBytesLeft == 0);
if (devState != Transfer_Data_Dma)
panic("Inconsistent device state for DMA start!\n");
- curPrdAddr = pciToDma((Addr)prdTableBase);
+ // PRD base address is given by bits 31:2
+ curPrdAddr = pciToDma((Addr)(prdTableBase & ~ULL(0x3)));
dmaState = Dma_Transfer;
uint32_t size = 0;
dmaRead = false;
- // copy the command to the shadow
- curCommand = cmdReg.command;
-
// Decode commands
switch (cmdReg.command) {
// Supported non-data commands
// Supported PIO data-in commands
case WIN_IDENTIFY:
- cmdBytesLeft = sizeof(struct hd_driveid);
+ cmdBytes = cmdBytesLeft = sizeof(struct hd_driveid);
devState = Prepare_Data_In;
action = ACT_DATA_READY;
break;
panic("Attempt to perform CHS access, only supports LBA\n");
if (cmdReg.sec_count == 0)
- cmdBytesLeft = (256 * SectorSize);
+ cmdBytes = cmdBytesLeft = (256 * SectorSize);
else
- cmdBytesLeft = (cmdReg.sec_count * SectorSize);
+ cmdBytes = cmdBytesLeft = (cmdReg.sec_count * SectorSize);
curSector = getLBABase();
panic("Attempt to perform CHS access, only supports LBA\n");
if (cmdReg.sec_count == 0)
- cmdBytesLeft = (256 * SectorSize);
+ cmdBytes = cmdBytesLeft = (256 * SectorSize);
else
- cmdBytesLeft = (cmdReg.sec_count * SectorSize);
+ cmdBytes = cmdBytesLeft = (cmdReg.sec_count * SectorSize);
curSector = getLBABase();
panic("Attempt to perform CHS access, only supports LBA\n");
if (cmdReg.sec_count == 0)
- cmdBytesLeft = (256 * SectorSize);
+ cmdBytes = cmdBytesLeft = (256 * SectorSize);
else
- cmdBytesLeft = (cmdReg.sec_count * SectorSize);
+ cmdBytes = cmdBytesLeft = (cmdReg.sec_count * SectorSize);
curSector = getLBABase();
if (action != ACT_NONE) {
// set the BSY bit
- cmdReg.status |= STATUS_BSY_BIT;
+ status |= STATUS_BSY_BIT;
// clear the DRQ bit
- cmdReg.status &= ~STATUS_DRQ_BIT;
+ status &= ~STATUS_DRQ_BIT;
+ // clear the DF bit
+ status &= ~STATUS_DF_BIT;
updateState(action);
}
IdeDisk::updateState(DevAction_t action)
{
switch (devState) {
+ case Device_Srst:
+ if (action == ACT_SRST_SET) {
+ // set the BSY bit
+ status |= STATUS_BSY_BIT;
+ } else if (action == ACT_SRST_CLEAR) {
+ // clear the BSY bit
+ status &= ~STATUS_BSY_BIT;
+
+ // reset the device state
+ reset(devID);
+ }
+ break;
+
case Device_Idle_S:
- if (!isDEVSelect())
+ if (action == ACT_SELECT_WRITE && !isDEVSelect()) {
devState = Device_Idle_NS;
- else if (action == ACT_CMD_WRITE)
+ } else if (action == ACT_CMD_WRITE) {
startCommand();
+ }
break;
case Device_Idle_SI:
- if (!isDEVSelect()) {
+ if (action == ACT_SELECT_WRITE && !isDEVSelect()) {
devState = Device_Idle_NS;
intrClear();
} else if (action == ACT_STAT_READ || isIENSet()) {
break;
case Device_Idle_NS:
- if (isDEVSelect()) {
+ if (action == ACT_SELECT_WRITE && isDEVSelect()) {
if (!isIENSet() && intrPending) {
devState = Device_Idle_SI;
intrPost();
}
} else if (action == ACT_DATA_READY) {
// clear the BSY bit
- cmdReg.status &= ~STATUS_BSY_BIT;
+ status &= ~STATUS_BSY_BIT;
// set the DRQ bit
- cmdReg.status |= STATUS_DRQ_BIT;
+ status |= STATUS_DRQ_BIT;
// copy the data into the data buffer
- if (curCommand == WIN_IDENTIFY) {
+ if (cmdReg.command == WIN_IDENTIFY) {
// Reset the drqBytes for this block
drqBytesLeft = sizeof(struct hd_driveid);
} else {
devState = Prepare_Data_In;
// set the BSY_BIT
- cmdReg.status |= STATUS_BSY_BIT;
+ status |= STATUS_BSY_BIT;
// clear the DRQ_BIT
- cmdReg.status &= ~STATUS_DRQ_BIT;
+ status &= ~STATUS_DRQ_BIT;
/** @todo change this to a scheduled event to simulate
disk delay */
} else {
devState = Device_Idle_S;
}
- } else if (cmdBytesLeft != 0) {
+ } else if (action == ACT_DATA_READY && cmdBytesLeft != 0) {
// clear the BSY bit
- cmdReg.status &= ~STATUS_BSY_BIT;
+ status &= ~STATUS_BSY_BIT;
// set the DRQ bit
- cmdReg.status |= STATUS_DRQ_BIT;
+ status |= STATUS_DRQ_BIT;
// clear the data buffer to get it ready for writes
memset(dataBuffer, 0, MAX_DMA_SIZE);
- if (!isIENSet()) {
+ // reset the drqBytes for this block
+ drqBytesLeft = SectorSize;
+
+ if (cmdBytesLeft == cmdBytes || isIENSet()) {
+ devState = Transfer_Data_Out;
+ } else {
devState = Data_Ready_INTRQ_Out;
intrPost();
- } else {
- devState = Transfer_Data_Out;
}
}
break;
writeDisk(curSector++, dataBuffer);
// set the BSY bit
- cmdReg.status |= STATUS_BSY_BIT;
+ status |= STATUS_BSY_BIT;
+ // set the seek bit
+ status |= STATUS_SEEK_BIT;
// clear the DRQ bit
- cmdReg.status &= ~STATUS_DRQ_BIT;
+ status &= ~STATUS_DRQ_BIT;
devState = Prepare_Data_Out;
}
} else if (action == ACT_DMA_READY) {
// clear the BSY bit
- cmdReg.status &= ~STATUS_BSY_BIT;
+ status &= ~STATUS_BSY_BIT;
// set the DRQ bit
- cmdReg.status |= STATUS_DRQ_BIT;
+ status |= STATUS_DRQ_BIT;
devState = Transfer_Data_Dma;
// clear the BSY bit
setComplete();
// set the seek bit
- cmdReg.status |= 0x10;
+ status |= STATUS_SEEK_BIT;
// clear the controller state for DMA transfer
ctrl->setDmaComplete(this);
Tick reschedule = 0;
Events_t event = None;
+ int eventCount = 0;
+
if (dmaTransferEvent.scheduled()) {
reschedule = dmaTransferEvent.when();
event = Transfer;
- } else if (dmaReadWaitEvent.scheduled()) {
+ eventCount++;
+ }
+ if (dmaReadWaitEvent.scheduled()) {
reschedule = dmaReadWaitEvent.when();
event = ReadWait;
- } else if (dmaWriteWaitEvent.scheduled()) {
+ eventCount++;
+ }
+ if (dmaWriteWaitEvent.scheduled()) {
reschedule = dmaWriteWaitEvent.when();
event = WriteWait;
- } else if (dmaPrdReadEvent.scheduled()) {
+ eventCount++;
+ }
+ if (dmaPrdReadEvent.scheduled()) {
reschedule = dmaPrdReadEvent.when();
event = PrdRead;
- } else if (dmaReadEvent.scheduled()) {
+ eventCount++;
+ }
+ if (dmaReadEvent.scheduled()) {
reschedule = dmaReadEvent.when();
event = DmaRead;
- } else if (dmaWriteEvent.scheduled()) {
+ eventCount++;
+ }
+ if (dmaWriteEvent.scheduled()) {
reschedule = dmaWriteEvent.when();
event = DmaWrite;
+ eventCount++;
}
+ assert(eventCount <= 1);
+
SERIALIZE_SCALAR(reschedule);
SERIALIZE_ENUM(event);
SERIALIZE_SCALAR(cmdReg.cyl_low);
SERIALIZE_SCALAR(cmdReg.cyl_high);
SERIALIZE_SCALAR(cmdReg.drive);
- SERIALIZE_SCALAR(cmdReg.status);
+ SERIALIZE_SCALAR(cmdReg.command);
+ SERIALIZE_SCALAR(status);
SERIALIZE_SCALAR(nIENBit);
SERIALIZE_SCALAR(devID);
// Serialize current transfer related information
SERIALIZE_SCALAR(cmdBytesLeft);
+ SERIALIZE_SCALAR(cmdBytes);
SERIALIZE_SCALAR(drqBytesLeft);
SERIALIZE_SCALAR(curSector);
- SERIALIZE_SCALAR(curCommand);
SERIALIZE_SCALAR(dmaRead);
SERIALIZE_SCALAR(dmaInterfaceBytes);
SERIALIZE_SCALAR(intrPending);
UNSERIALIZE_SCALAR(cmdReg.cyl_low);
UNSERIALIZE_SCALAR(cmdReg.cyl_high);
UNSERIALIZE_SCALAR(cmdReg.drive);
- UNSERIALIZE_SCALAR(cmdReg.status);
+ UNSERIALIZE_SCALAR(cmdReg.command);
+ UNSERIALIZE_SCALAR(status);
UNSERIALIZE_SCALAR(nIENBit);
UNSERIALIZE_SCALAR(devID);
UNSERIALIZE_SCALAR(curPrdAddr);
// Unserialize current transfer related information
+ UNSERIALIZE_SCALAR(cmdBytes);
UNSERIALIZE_SCALAR(cmdBytesLeft);
UNSERIALIZE_SCALAR(drqBytesLeft);
UNSERIALIZE_SCALAR(curSector);
- UNSERIALIZE_SCALAR(curCommand);
UNSERIALIZE_SCALAR(dmaRead);
UNSERIALIZE_SCALAR(dmaInterfaceBytes);
UNSERIALIZE_SCALAR(intrPending);
projects / gem5.git / blobdiff