Changed the hello_sparc executable back to the cross compiled one

[gem5.git] / dev / ns_gige.cc

diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 07bf178fc4b8ea4bb87cb168af026b4c333e2c3e..f7e67811c03584ff38de1e843be41ab627ac9465 100644 (file)
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -34,6 +34,7 @@
 #include <deque>
 #include <string>
 
+#include "arch/alpha/ev5.hh"
 #include "base/inet.hh"
 #include "cpu/exec_context.hh"
 #include "dev/etherlink.hh"
@@ -49,7 +50,7 @@
 #include "sim/debug.hh"
 #include "sim/host.hh"
 #include "sim/stats.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/vtophys.hh"
 
 const char *NsRxStateStrings[] =
 {
@@ -131,8 +132,6 @@ NSGigE::NSGigE(Params *p)
     } else if (p->payload_bus)
         panic("Must define a header bus if defining a payload bus");
 
-    pioDelayWrite = p->pio_delay_write && pioInterface;
-
     intrDelay = p->intr_delay;
     dmaReadDelay = p->dma_read_delay;
     dmaWriteDelay = p->dma_write_delay;
@@ -559,7 +558,7 @@ NSGigE::writeConfig(int offset, int size, const uint8_t* data)
  * This reads the device registers, which are detailed in the NS83820
  * spec sheet
  */
-Fault *
+Fault
 NSGigE::read(MemReqPtr &req, uint8_t *data)
 {
     assert(ioEnable);
@@ -769,6 +768,8 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
                     reg |= M5REG_RX_THREAD;
                 if (params()->tx_thread)
                     reg |= M5REG_TX_THREAD;
+                if (params()->rss)
+                    reg |= M5REG_RSS;
                 break;
 
               default:
@@ -788,7 +789,7 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
     return NoFault;
 }
 
-Fault *
+Fault
 NSGigE::write(MemReqPtr &req, const uint8_t *data)
 {
     assert(ioEnable);
@@ -805,13 +806,6 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
     } else if (daddr > 0x3FC)
         panic("Something is messed up!\n");
 
-    if (pioDelayWrite) {
-        int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
-        if (cpu >= writeQueue.size())
-            writeQueue.resize(cpu + 1);
-        writeQueue[cpu].push_back(RegWriteData(daddr, *(uint32_t *)data));
-    }
-
     if (req->size == sizeof(uint32_t)) {
         uint32_t reg = *(uint32_t *)data;
         uint16_t rfaddr;
@@ -824,24 +818,20 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
             if (reg & CR_TXD) {
                 txEnable = false;
             } else if (reg & CR_TXE) {
-                if (!pioDelayWrite) {
-                    txEnable = true;
+                txEnable = true;
 
-                    // the kernel is enabling the transmit machine
-                    if (txState == txIdle)
-                        txKick();
-                }
+                // the kernel is enabling the transmit machine
+                if (txState == txIdle)
+                    txKick();
             }
 
             if (reg & CR_RXD) {
                 rxEnable = false;
             } else if (reg & CR_RXE) {
-                if (!pioDelayWrite) {
-                    rxEnable = true;
+                rxEnable = true;
 
-                    if (rxState == rxIdle)
-                        rxKick();
-                }
+                if (rxState == rxIdle)
+                    rxKick();
             }
 
             if (reg & CR_TXR)
@@ -2949,38 +2939,9 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
 Tick
 NSGigE::cacheAccess(MemReqPtr &req)
 {
-    Addr daddr = req->paddr & 0xfff;
     DPRINTF(EthernetPIO, "timing access to paddr=%#x (daddr=%#x)\n",
-            req->paddr, daddr);
-
-    if (!pioDelayWrite || !req->cmd.isWrite())
-        return curTick + pioLatency;
-
-    int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
-    std::list<RegWriteData> &wq = writeQueue[cpu];
-    if (wq.empty())
-        panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr);
-
-    const RegWriteData &data = wq.front();
-    if (data.daddr != daddr)
-        panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x",
-              cpu, data.daddr, daddr);
-
-    if (daddr == CR) {
-        if ((data.value & (CR_TXD | CR_TXE)) == CR_TXE) {
-            txEnable = true;
-            if (txState == txIdle)
-                txKick();
-        }
-
-        if ((data.value & (CR_RXD | CR_RXE)) == CR_RXE) {
-            rxEnable = true;
-            if (rxState == rxIdle)
-                rxKick();
-        }
-    }
+            req->paddr, req->paddr & 0xfff);
 
-    wq.pop_front();
     return curTick + pioLatency;
 }
 
@@ -3040,7 +3001,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
     Param<Tick> dma_write_factor;
     Param<bool> dma_no_allocate;
     Param<Tick> pio_latency;
-    Param<bool> pio_delay_write;
     Param<Tick> intr_delay;
 
     Param<Tick> rx_delay;
@@ -3052,6 +3012,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
     Param<string> hardware_address;
     Param<bool> rx_thread;
     Param<bool> tx_thread;
+    Param<bool> rss;
 
 END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
 
@@ -3081,7 +3042,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
     INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
     INIT_PARAM(dma_no_allocate, "Should DMA reads allocate cache lines"),
     INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"),
-    INIT_PARAM(pio_delay_write, ""),
     INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
 
     INIT_PARAM(rx_delay, "Receive Delay"),
@@ -3092,7 +3052,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
     INIT_PARAM(rx_filter, "Enable Receive Filter"),
     INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
     INIT_PARAM(rx_thread, ""),
-    INIT_PARAM(tx_thread, "")
+    INIT_PARAM(tx_thread, ""),
+    INIT_PARAM(rss, "")
 
 END_INIT_SIM_OBJECT_PARAMS(NSGigE)
 
@@ -3126,7 +3087,6 @@ CREATE_SIM_OBJECT(NSGigE)
     params->dma_write_factor = dma_write_factor;
     params->dma_no_allocate = dma_no_allocate;
     params->pio_latency = pio_latency;
-    params->pio_delay_write = pio_delay_write;
     params->intr_delay = intr_delay;
 
     params->rx_delay = rx_delay;
@@ -3138,6 +3098,7 @@ CREATE_SIM_OBJECT(NSGigE)
     params->eaddr = hardware_address;
     params->rx_thread = rx_thread;
     params->tx_thread = tx_thread;
+    params->rss = rss;
 
     return new NSGigE(params);
 }