#include <deque>
#include <string>
+#include "arch/alpha/ev5.hh"
#include "base/inet.hh"
#include "cpu/exec_context.hh"
#include "dev/etherlink.hh"
#include "sim/debug.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/vtophys.hh"
const char *NsRxStateStrings[] =
{
using namespace std;
using namespace Net;
+using namespace TheISA;
///////////////////////////////////////////////////////////////////////
//
physmem(p->pmem), intrTick(0), cpuPendingIntr(false),
intrEvent(0), interface(0)
{
- if (p->header_bus) {
+ if (p->pio_bus) {
pioInterface = newPioInterface(name() + ".pio", p->hier,
- p->header_bus, this,
+ p->pio_bus, this,
&NSGigE::cacheAccess);
+ pioLatency = p->pio_latency * p->pio_bus->clockRate;
+ }
- pioLatency = p->pio_latency * p->header_bus->clockRate;
-
+ if (p->header_bus) {
if (p->payload_bus)
dmaInterface = new DMAInterface<Bus>(name() + ".dma",
p->header_bus,
p->header_bus,
p->header_bus, 1,
p->dma_no_allocate);
- } else if (p->payload_bus) {
- pioInterface = newPioInterface(name() + ".pio2", p->hier,
- p->payload_bus, this,
- &NSGigE::cacheAccess);
-
- pioLatency = p->pio_latency * p->payload_bus->clockRate;
-
- dmaInterface = new DMAInterface<Bus>(name() + ".dma",
- p->payload_bus,
- p->payload_bus, 1,
- p->dma_no_allocate);
- }
-
+ } else if (p->payload_bus)
+ panic("Must define a header bus if defining a payload bus");
intrDelay = p->intr_delay;
dmaReadDelay = p->dma_read_delay;
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
readConfig(daddr & 0xff, req->size, data);
- return No_Fault;
+ return NoFault;
} else if (daddr >= MIB_START && daddr <= MIB_END) {
// don't implement all the MIB's. hopefully the kernel
// doesn't actually DEPEND upon their values
// MIB are just hardware stats keepers
uint32_t ® = *(uint32_t *) data;
reg = 0;
- return No_Fault;
+ return NoFault;
} else if (daddr > 0x3FC)
panic("Something is messed up!\n");
case M5REG:
reg = 0;
- if (params()->dedicated)
- reg |= M5REG_DEDICATED;
+ if (params()->rx_thread)
+ reg |= M5REG_RX_THREAD;
+ if (params()->tx_thread)
+ reg |= M5REG_TX_THREAD;
+ if (params()->rss)
+ reg |= M5REG_RSS;
break;
default:
daddr, req->size);
}
- return No_Fault;
+ return NoFault;
}
Fault
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
writeConfig(daddr & 0xff, req->size, data);
- return No_Fault;
+ return NoFault;
} else if (daddr > 0x3FC)
panic("Something is messed up!\n");
panic("Invalid Request Size");
}
- return No_Fault;
+ return NoFault;
}
void
NSGigE::cacheAccess(MemReqPtr &req)
{
DPRINTF(EthernetPIO, "timing access to paddr=%#x (daddr=%#x)\n",
- req->paddr, req->paddr - addr);
+ req->paddr, req->paddr & 0xfff);
+
return curTick + pioLatency;
}
Param<uint32_t> pci_func;
SimObjectParam<HierParams *> hier;
- SimObjectParam<Bus*> io_bus;
+ SimObjectParam<Bus*> pio_bus;
+ SimObjectParam<Bus*> dma_bus;
SimObjectParam<Bus*> payload_bus;
Param<bool> dma_desc_free;
Param<bool> dma_data_free;
Param<bool> rx_filter;
Param<string> hardware_address;
- Param<bool> dedicated;
+ Param<bool> rx_thread;
+ Param<bool> tx_thread;
+ Param<bool> rss;
END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM(hier, "Hierarchy global variables"),
- INIT_PARAM(io_bus, "The IO Bus to attach to for headers"),
+ INIT_PARAM(pio_bus, ""),
+ INIT_PARAM(dma_bus, ""),
INIT_PARAM(payload_bus, "The IO Bus to attach to for payload"),
INIT_PARAM(dma_desc_free, "DMA of Descriptors is free"),
INIT_PARAM(dma_data_free, "DMA of Data is free"),
INIT_PARAM(rx_filter, "Enable Receive Filter"),
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
- INIT_PARAM(dedicated, "dedicate a kernel thread to the driver")
+ INIT_PARAM(rx_thread, ""),
+ INIT_PARAM(tx_thread, ""),
+ INIT_PARAM(rss, "")
END_INIT_SIM_OBJECT_PARAMS(NSGigE)
params->functionNum = pci_func;
params->hier = hier;
- params->header_bus = io_bus;
+ params->pio_bus = pio_bus;
+ params->header_bus = dma_bus;
params->payload_bus = payload_bus;
params->dma_desc_free = dma_desc_free;
params->dma_data_free = dma_data_free;
params->rx_filter = rx_filter;
params->eaddr = hardware_address;
- params->dedicated = dedicated;
+ params->rx_thread = rx_thread;
+ params->tx_thread = tx_thread;
+ params->rss = rss;
return new NSGigE(params);
}