Changed the hello_sparc executable back to the cross compiled one

[gem5.git] / dev / ns_gige.cc

diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index f6d15b02fa18d56b268506e7852a64213567760e..f7e67811c03584ff38de1e843be41ab627ac9465 100644 (file)
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -34,6 +34,7 @@
 #include <deque>
 #include <string>
 
+#include "arch/alpha/ev5.hh"
 #include "base/inet.hh"
 #include "cpu/exec_context.hh"
 #include "dev/etherlink.hh"
@@ -49,7 +50,7 @@
 #include "sim/debug.hh"
 #include "sim/host.hh"
 #include "sim/stats.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/vtophys.hh"
 
 const char *NsRxStateStrings[] =
 {
@@ -84,6 +85,7 @@ const char *NsDmaState[] =
 
 using namespace std;
 using namespace Net;
+using namespace TheISA;
 
 ///////////////////////////////////////////////////////////////////////
 //
@@ -109,13 +111,14 @@ NSGigE::NSGigE(Params *p)
       physmem(p->pmem), intrTick(0), cpuPendingIntr(false),
       intrEvent(0), interface(0)
 {
-    if (p->header_bus) {
+    if (p->pio_bus) {
         pioInterface = newPioInterface(name() + ".pio", p->hier,
-                                       p->header_bus, this,
+                                       p->pio_bus, this,
                                        &NSGigE::cacheAccess);
+        pioLatency = p->pio_latency * p->pio_bus->clockRate;
+    }
 
-        pioLatency = p->pio_latency * p->header_bus->clockRate;
-
+    if (p->header_bus) {
         if (p->payload_bus)
             dmaInterface = new DMAInterface<Bus>(name() + ".dma",
                                                  p->header_bus,
@@ -126,19 +129,8 @@ NSGigE::NSGigE(Params *p)
                                                  p->header_bus,
                                                  p->header_bus, 1,
                                                  p->dma_no_allocate);
-    } else if (p->payload_bus) {
-        pioInterface = newPioInterface(name() + ".pio2", p->hier,
-                                       p->payload_bus, this,
-                                       &NSGigE::cacheAccess);
-
-        pioLatency = p->pio_latency * p->payload_bus->clockRate;
-
-        dmaInterface = new DMAInterface<Bus>(name() + ".dma",
-                                             p->payload_bus,
-                                             p->payload_bus, 1,
-                                             p->dma_no_allocate);
-    }
-
+    } else if (p->payload_bus)
+        panic("Must define a header bus if defining a payload bus");
 
     intrDelay = p->intr_delay;
     dmaReadDelay = p->dma_read_delay;
@@ -583,14 +575,14 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
         panic("Accessing reserved register");
     } else if (daddr > RESERVED && daddr <= 0x3FC) {
         readConfig(daddr & 0xff, req->size, data);
-        return No_Fault;
+        return NoFault;
     } else if (daddr >= MIB_START && daddr <= MIB_END) {
         // don't implement all the MIB's.  hopefully the kernel
         // doesn't actually DEPEND upon their values
         // MIB are just hardware stats keepers
         uint32_t &reg = *(uint32_t *) data;
         reg = 0;
-        return No_Fault;
+        return NoFault;
     } else if (daddr > 0x3FC)
         panic("Something is messed up!\n");
 
@@ -772,8 +764,12 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
 
               case M5REG:
                 reg = 0;
-                if (params()->dedicated)
-                    reg |= M5REG_DEDICATED;
+                if (params()->rx_thread)
+                    reg |= M5REG_RX_THREAD;
+                if (params()->tx_thread)
+                    reg |= M5REG_TX_THREAD;
+                if (params()->rss)
+                    reg |= M5REG_RSS;
                 break;
 
               default:
@@ -790,7 +786,7 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
               daddr, req->size);
     }
 
-    return No_Fault;
+    return NoFault;
 }
 
 Fault
@@ -806,7 +802,7 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
         panic("Accessing reserved register");
     } else if (daddr > RESERVED && daddr <= 0x3FC) {
         writeConfig(daddr & 0xff, req->size, data);
-        return No_Fault;
+        return NoFault;
     } else if (daddr > 0x3FC)
         panic("Something is messed up!\n");
 
@@ -1198,7 +1194,7 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
         panic("Invalid Request Size");
     }
 
-    return No_Fault;
+    return NoFault;
 }
 
 void
@@ -2531,20 +2527,17 @@ NSGigE::recvPacket(PacketPtr packet)
 
     if (!rxEnable) {
         DPRINTF(Ethernet, "receive disabled...packet dropped\n");
-        interface->recvDone();
         return true;
     }
 
     if (!rxFilterEnable) {
         DPRINTF(Ethernet,
             "receive packet filtering disabled . . . packet dropped\n");
-        interface->recvDone();
         return true;
     }
 
     if (rxFilter(packet)) {
         DPRINTF(Ethernet, "packet filtered...dropped\n");
-        interface->recvDone();
         return true;
     }
 
@@ -2567,7 +2560,6 @@ NSGigE::recvPacket(PacketPtr packet)
     }
 
     rxFifo.push(packet);
-    interface->recvDone();
 
     rxKick();
     return true;
@@ -2948,7 +2940,8 @@ Tick
 NSGigE::cacheAccess(MemReqPtr &req)
 {
     DPRINTF(EthernetPIO, "timing access to paddr=%#x (daddr=%#x)\n",
-            req->paddr, req->paddr - addr);
+            req->paddr, req->paddr & 0xfff);
+
     return curTick + pioLatency;
 }
 
@@ -2997,7 +2990,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
     Param<uint32_t> pci_func;
 
     SimObjectParam<HierParams *> hier;
-    SimObjectParam<Bus*> io_bus;
+    SimObjectParam<Bus*> pio_bus;
+    SimObjectParam<Bus*> dma_bus;
     SimObjectParam<Bus*> payload_bus;
     Param<bool> dma_desc_free;
     Param<bool> dma_data_free;
@@ -3016,7 +3010,9 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
 
     Param<bool> rx_filter;
     Param<string> hardware_address;
-    Param<bool> dedicated;
+    Param<bool> rx_thread;
+    Param<bool> tx_thread;
+    Param<bool> rss;
 
 END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
 
@@ -3035,7 +3031,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
     INIT_PARAM(pci_func, "PCI function code"),
 
     INIT_PARAM(hier, "Hierarchy global variables"),
-    INIT_PARAM(io_bus, "The IO Bus to attach to for headers"),
+    INIT_PARAM(pio_bus, ""),
+    INIT_PARAM(dma_bus, ""),
     INIT_PARAM(payload_bus, "The IO Bus to attach to for payload"),
     INIT_PARAM(dma_desc_free, "DMA of Descriptors is free"),
     INIT_PARAM(dma_data_free, "DMA of Data is free"),
@@ -3054,7 +3051,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
 
     INIT_PARAM(rx_filter, "Enable Receive Filter"),
     INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
-    INIT_PARAM(dedicated, "dedicate a kernel thread to the driver")
+    INIT_PARAM(rx_thread, ""),
+    INIT_PARAM(tx_thread, ""),
+    INIT_PARAM(rss, "")
 
 END_INIT_SIM_OBJECT_PARAMS(NSGigE)
 
@@ -3077,7 +3076,8 @@ CREATE_SIM_OBJECT(NSGigE)
     params->functionNum = pci_func;
 
     params->hier = hier;
-    params->header_bus = io_bus;
+    params->pio_bus = pio_bus;
+    params->header_bus = dma_bus;
     params->payload_bus = payload_bus;
     params->dma_desc_free = dma_desc_free;
     params->dma_data_free = dma_data_free;
@@ -3096,7 +3096,9 @@ CREATE_SIM_OBJECT(NSGigE)
 
     params->rx_filter = rx_filter;
     params->eaddr = hardware_address;
-    params->dedicated = dedicated;
+    params->rx_thread = rx_thread;
+    params->tx_thread = tx_thread;
+    params->rss = rss;
 
     return new NSGigE(params);
 }