/*
- * Copyright (c) 2004 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* Device module for modelling the National Semiconductor
* DP83820 ethernet controller
*/
#include "dev/io_device.hh"
#include "dev/ns_gige_reg.h"
#include "dev/pcidev.hh"
+#include "dev/pktfifo.hh"
#include "mem/bus/bus.hh"
#include "sim/eventq.hh"
+// Hash filtering constants
+const uint16_t FHASH_ADDR = 0x100;
+const uint16_t FHASH_SIZE = 0x100;
+
+// EEPROM constants
+const uint8_t EEPROM_READ = 0x2;
+const uint8_t EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM
+const uint8_t EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2
+const uint8_t EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1
+const uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
+
/**
* Ethernet device registers
*/
uint32_t pcr;
uint32_t rfcr;
uint32_t rfdr;
+ uint32_t brar;
+ uint32_t brdr;
uint32_t srr;
uint32_t mibc;
uint32_t vrcr;
* the linux driver doesn't use any other ROM
*/
uint8_t perfectMatch[ETH_ADDR_LEN];
+
+ /**
+ * for hash table memory.
+ * used by the freebsd driver
+ */
+ uint8_t filterHash[FHASH_SIZE];
};
-class IntrControl;
class NSGigEInt;
class PhysicalMemory;
class BaseInterface;
class PciConfigAll;
/**
- * NS DP82830 Ethernet device model
+ * NS DP83820 Ethernet device model
*/
class NSGigE : public PciDev
{
dmaWriteWaiting
};
+ /** EEPROM State Machine States */
+ enum EEPROMState
+ {
+ eepromStart,
+ eepromGetOpcode,
+ eepromGetAddress,
+ eepromRead
+ };
+
private:
Addr addr;
static const Addr size = sizeof(dp_regs);
protected:
- typedef std::deque<PacketPtr> pktbuf_t;
- typedef pktbuf_t::iterator pktiter_t;
-
/** device register file */
dp_regs regs;
dp_rom rom;
/*** BASIC STRUCTURES FOR TX/RX ***/
/* Data FIFOs */
- pktbuf_t txFifo;
- uint32_t maxTxFifoSize;
- pktbuf_t rxFifo;
- uint32_t maxRxFifoSize;
+ PacketFifo txFifo;
+ PacketFifo rxFifo;
/** various helper vars */
PacketPtr txPacket;
bool txDmaFree;
/** DescCaches */
- ns_desc txDescCache;
- ns_desc rxDescCache;
+ ns_desc32 txDesc32;
+ ns_desc32 rxDesc32;
+ ns_desc64 txDesc64;
+ ns_desc64 rxDesc64;
+
+ /* state machine cycle time */
+ Tick clock;
+ inline Tick cycles(int numCycles) const { return numCycles * clock; }
/* tx State Machine */
TxState txState;
/** Current Transmit Descriptor Done */
bool CTDD;
- /** current amt of free space in txDataFifo in bytes */
- uint32_t txFifoAvail;
/** halt the tx state machine after next packet */
bool txHalt;
/** ptr to the next byte in the current fragment */
bool CRDD;
/** num of bytes in the current packet being drained from rxDataFifo */
uint32_t rxPktBytes;
- /** number of bytes in the rxFifo */
- uint32_t rxFifoCnt;
/** halt the rx state machine after current packet */
bool rxHalt;
/** ptr to the next byte in current fragment */
uint32_t rxDescCnt;
DmaState rxDmaState;
+ struct RegWriteData {
+ Addr daddr;
+ uint32_t value;
+ RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {}
+ };
+
+ std::vector<std::list<RegWriteData> > writeQueue;
+ bool pioDelayWrite;
+
bool extstsEnable;
+ /** EEPROM State Machine */
+ EEPROMState eepromState;
+ bool eepromClk;
+ uint8_t eepromBitsToRx;
+ uint8_t eepromOpcode;
+ uint8_t eepromAddress;
+ uint16_t eepromData;
+
protected:
Tick dmaReadDelay;
Tick dmaWriteDelay;
bool dmaDescFree;
bool dmaDataFree;
-
protected:
Tick txDelay;
Tick rxDelay;
void rxKick();
Tick rxKickTick;
typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
- friend class RxKickEvent;
+ friend void RxKickEvent::process();
+ RxKickEvent rxKickEvent;
void txKick();
Tick txKickTick;
typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
- friend class TxKickEvent;
+ friend void TxKickEvent::process();
+ TxKickEvent txKickEvent;
+
+ void eepromKick();
/**
* Retransmit event
txKick();
}
typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
- friend class TxEvent;
+ friend void TxEvent::process();
TxEvent txEvent;
void txDump() const;
* receive address filter
*/
bool rxFilterEnable;
- bool rxFilter(PacketPtr &packet);
+ bool rxFilter(const PacketPtr &packet);
bool acceptBroadcast;
bool acceptMulticast;
bool acceptUnicast;
bool acceptPerfect;
bool acceptArp;
+ bool multicastHashEnable;
PhysicalMemory *physmem;
/**
* Interrupt management
*/
- IntrControl *intctrl;
void devIntrPost(uint32_t interrupts);
void devIntrClear(uint32_t interrupts);
void devIntrChangeMask();
void cpuIntrClear();
typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
- friend class IntrEvent;
+ friend void IntrEvent::process();
IntrEvent *intrEvent;
NSGigEInt *interface;
{
PhysicalMemory *pmem;
HierParams *hier;
+ Bus *pio_bus;
Bus *header_bus;
Bus *payload_bus;
+ Tick clock;
Tick intr_delay;
Tick tx_delay;
Tick rx_delay;
Tick pio_latency;
+ bool pio_delay_write;
bool dma_desc_free;
bool dma_data_free;
Tick dma_read_delay;
Net::EthAddr eaddr;
uint32_t tx_fifo_size;
uint32_t rx_fifo_size;
+ bool rx_thread;
+ bool tx_thread;
+ bool dma_no_allocate;
};
NSGigE(Params *params);
~NSGigE();
const Params *params() const { return (const Params *)_params; }
- virtual void WriteConfig(int offset, int size, uint32_t data);
- virtual void ReadConfig(int offset, int size, uint8_t *data);
+ virtual void writeConfig(int offset, int size, const uint8_t *data);
+ virtual void readConfig(int offset, int size, uint8_t *data);
- virtual Fault read(MemReqPtr &req, uint8_t *data);
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }
- bool recvPacket(PacketPtr &packet);
+ bool recvPacket(PacketPtr packet);
void transferDone();
void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
Stats::Scalar<> descDmaWrites;
Stats::Scalar<> descDmaRdBytes;
Stats::Scalar<> descDmaWrBytes;
+ Stats::Formula totBandwidth;
+ Stats::Formula totPackets;
+ Stats::Formula totBytes;
+ Stats::Formula totPacketRate;
Stats::Formula txBandwidth;
Stats::Formula rxBandwidth;
Stats::Formula txPacketRate;
Stats::Formula rxPacketRate;
+ Stats::Scalar<> postedSwi;
+ Stats::Formula coalescedSwi;
+ Stats::Scalar<> totalSwi;
+ Stats::Scalar<> postedRxIdle;
+ Stats::Formula coalescedRxIdle;
+ Stats::Scalar<> totalRxIdle;
+ Stats::Scalar<> postedRxOk;
+ Stats::Formula coalescedRxOk;
+ Stats::Scalar<> totalRxOk;
+ Stats::Scalar<> postedRxDesc;
+ Stats::Formula coalescedRxDesc;
+ Stats::Scalar<> totalRxDesc;
+ Stats::Scalar<> postedTxOk;
+ Stats::Formula coalescedTxOk;
+ Stats::Scalar<> totalTxOk;
+ Stats::Scalar<> postedTxIdle;
+ Stats::Formula coalescedTxIdle;
+ Stats::Scalar<> totalTxIdle;
+ Stats::Scalar<> postedTxDesc;
+ Stats::Formula coalescedTxDesc;
+ Stats::Scalar<> totalTxDesc;
+ Stats::Scalar<> postedRxOrn;
+ Stats::Formula coalescedRxOrn;
+ Stats::Scalar<> totalRxOrn;
+ Stats::Formula coalescedTotal;
+ Stats::Scalar<> postedInterrupts;
+ Stats::Scalar<> droppedPackets;
public:
Tick cacheAccess(MemReqPtr &req);
NSGigEInt(const std::string &name, NSGigE *d)
: EtherInt(name), dev(d) { dev->setInterface(this); }
- virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); }
+ virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
virtual void sendDone() { dev->transferDone(); }
};
projects / gem5.git / blobdiff