static const Addr size = sizeof(dp_regs);
protected:
- typedef std::deque<PacketPtr> pktbuf_t;
- typedef pktbuf_t::iterator pktiter_t;
-
/** device register file */
dp_regs regs;
dp_rom rom;
uint32_t rxDescCnt;
DmaState rxDmaState;
+ struct RegWriteData {
+ Addr daddr;
+ uint32_t value;
+ RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {}
+ };
+
+ std::vector<std::list<RegWriteData> > writeQueue;
+ bool pioDelayWrite;
+
bool extstsEnable;
/** EEPROM State Machine */
{
PhysicalMemory *pmem;
HierParams *hier;
+ Bus *pio_bus;
Bus *header_bus;
Bus *payload_bus;
Tick clock;
Tick tx_delay;
Tick rx_delay;
Tick pio_latency;
+ bool pio_delay_write;
bool dma_desc_free;
bool dma_data_free;
Tick dma_read_delay;
Net::EthAddr eaddr;
uint32_t tx_fifo_size;
uint32_t rx_fifo_size;
- bool dedicated;
+ bool rx_thread;
+ bool tx_thread;
bool dma_no_allocate;
};
virtual void writeConfig(int offset, int size, const uint8_t *data);
virtual void readConfig(int offset, int size, uint8_t *data);
- virtual Fault read(MemReqPtr &req, uint8_t *data);
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }