Get rid of deque (poor memory allocation), switch them over to lists.

[gem5.git] / dev / ns_gige.hh

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index b6554e5d6a76bded0462f0e361854638392bc5ff..181837c8df5d241971eab37b012734b906ee300d 100644 (file)
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -170,9 +170,6 @@ class NSGigE : public PciDev
     static const Addr size = sizeof(dp_regs);
 
   protected:
-    typedef std::deque<PacketPtr> pktbuf_t;
-    typedef pktbuf_t::iterator pktiter_t;
-
     /** device register file */
     dp_regs regs;
     dp_rom rom;
@@ -200,8 +197,10 @@ class NSGigE : public PciDev
     bool txDmaFree;
 
     /** DescCaches */
-    ns_desc txDescCache;
-    ns_desc rxDescCache;
+    ns_desc32 txDesc32;
+    ns_desc32 rxDesc32;
+    ns_desc64 txDesc64;
+    ns_desc64 rxDesc64;
 
     /* state machine cycle time */
     Tick clock;
@@ -237,6 +236,15 @@ class NSGigE : public PciDev
     uint32_t rxDescCnt;
     DmaState rxDmaState;
 
+    struct RegWriteData {
+        Addr daddr;
+        uint32_t value;
+        RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {}
+    };
+
+    std::vector<std::list<RegWriteData> > writeQueue;
+    bool pioDelayWrite;
+
     bool extstsEnable;
 
     /** EEPROM State Machine */
@@ -289,7 +297,6 @@ class NSGigE : public PciDev
     bool dmaDescFree;
     bool dmaDataFree;
 
-
   protected:
     Tick txDelay;
     Tick rxDelay;
@@ -367,6 +374,7 @@ class NSGigE : public PciDev
     {
         PhysicalMemory *pmem;
         HierParams *hier;
+        Bus *pio_bus;
         Bus *header_bus;
         Bus *payload_bus;
         Tick clock;
@@ -374,6 +382,7 @@ class NSGigE : public PciDev
         Tick tx_delay;
         Tick rx_delay;
         Tick pio_latency;
+        bool pio_delay_write;
         bool dma_desc_free;
         bool dma_data_free;
         Tick dma_read_delay;
@@ -384,7 +393,8 @@ class NSGigE : public PciDev
         Net::EthAddr eaddr;
         uint32_t tx_fifo_size;
         uint32_t rx_fifo_size;
-        uint32_t m5reg;
+        bool rx_thread;
+        bool tx_thread;
         bool dma_no_allocate;
     };
 
@@ -392,11 +402,11 @@ class NSGigE : public PciDev
     ~NSGigE();
     const Params *params() const { return (const Params *)_params; }
 
-    virtual void WriteConfig(int offset, int size, uint32_t data);
-    virtual void ReadConfig(int offset, int size, uint8_t *data);
+    virtual void writeConfig(int offset, int size, const uint8_t *data);
+    virtual void readConfig(int offset, int size, uint8_t *data);
 
-    virtual Fault read(MemReqPtr &req, uint8_t *data);
-    virtual Fault write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault * read(MemReqPtr &req, uint8_t *data);
+    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
 
     bool cpuIntrPending() const;
     void cpuIntrAck() { cpuIntrClear(); }