/*
- * Copyright (c) 2004 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* Device module for modelling the National Semiconductor
* DP83820 ethernet controller
*/
class PciConfigAll;
/**
- * NS DP82830 Ethernet device model
+ * NS DP83820 Ethernet device model
*/
class NSGigE : public PciDev
{
ns_desc txDescCache;
ns_desc rxDescCache;
+ /* state machine cycle time */
+ Tick clock;
+ inline Tick cycles(int numCycles) const { return numCycles * clock; }
+
/* tx State Machine */
TxState txState;
bool txEnable;
Tick rxKickTick;
typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
friend void RxKickEvent::process();
+ RxKickEvent rxKickEvent;
void txKick();
Tick txKickTick;
typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
friend void TxKickEvent::process();
+ TxKickEvent txKickEvent;
/**
* Retransmit event
HierParams *hier;
Bus *header_bus;
Bus *payload_bus;
+ Tick clock;
Tick intr_delay;
Tick tx_delay;
Tick rx_delay;
Net::EthAddr eaddr;
uint32_t tx_fifo_size;
uint32_t rx_fifo_size;
+ uint32_t m5reg;
+ bool dma_no_allocate;
};
NSGigE(Params *params);