Merge m5read@m5.eecs.umich.edu:/bk/m5

[gem5.git] / dev / ns_gige.hh

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 90711d63fc3e72e4b908d5d553187e1548a0ce0e..67f1b7ef5bb995e2f2e3da8a9083450dcfb59f92 100644 (file)
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2004 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Device module for modelling the National Semiconductor
  * DP83820 ethernet controller
  */
@@ -91,7 +91,6 @@ struct dp_rom {
     uint8_t perfectMatch[ETH_ADDR_LEN];
 };
 
-class IntrControl;
 class NSGigEInt;
 class PhysicalMemory;
 class BaseInterface;
@@ -100,7 +99,7 @@ class Bus;
 class PciConfigAll;
 
 /**
- * NS DP82830 Ethernet device model
+ * NS DP83820 Ethernet device model
  */
 class NSGigE : public PciDev
 {
@@ -176,6 +175,10 @@ class NSGigE : public PciDev
     ns_desc txDescCache;
     ns_desc rxDescCache;
 
+    /* state machine cycle time */
+    Tick clock;
+    inline Tick cycles(int numCycles) const { return numCycles * clock; }
+
     /* tx State Machine */
     TxState txState;
     bool txEnable;
@@ -262,12 +265,14 @@ class NSGigE : public PciDev
     void rxKick();
     Tick rxKickTick;
     typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
-    friend class RxKickEvent;
+    friend void RxKickEvent::process();
+    RxKickEvent rxKickEvent;
 
     void txKick();
     Tick txKickTick;
     typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
-    friend class TxKickEvent;
+    friend void TxKickEvent::process();
+    TxKickEvent txKickEvent;
 
     /**
      * Retransmit event
@@ -280,7 +285,7 @@ class NSGigE : public PciDev
             txKick();
     }
     typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
-    friend class TxEvent;
+    friend void TxEvent::process();
     TxEvent txEvent;
 
     void txDump() const;
@@ -302,7 +307,6 @@ class NSGigE : public PciDev
     /**
      * Interrupt management
      */
-    IntrControl *intctrl;
     void devIntrPost(uint32_t interrupts);
     void devIntrClear(uint32_t interrupts);
     void devIntrChangeMask();
@@ -315,7 +319,7 @@ class NSGigE : public PciDev
     void cpuIntrClear();
 
     typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
-    friend class IntrEvent;
+    friend void IntrEvent::process();
     IntrEvent *intrEvent;
     NSGigEInt *interface;
 
@@ -326,6 +330,7 @@ class NSGigE : public PciDev
         HierParams *hier;
         Bus *header_bus;
         Bus *payload_bus;
+        Tick clock;
         Tick intr_delay;
         Tick tx_delay;
         Tick rx_delay;
@@ -340,6 +345,8 @@ class NSGigE : public PciDev
         Net::EthAddr eaddr;
         uint32_t tx_fifo_size;
         uint32_t rx_fifo_size;
+        uint32_t m5reg;
+        bool dma_no_allocate;
     };
 
     NSGigE(Params *params);
@@ -381,10 +388,41 @@ class NSGigE : public PciDev
     Stats::Scalar<> descDmaWrites;
     Stats::Scalar<> descDmaRdBytes;
     Stats::Scalar<> descDmaWrBytes;
+    Stats::Formula totBandwidth;
+    Stats::Formula totPackets;
+    Stats::Formula totBytes;
+    Stats::Formula totPacketRate;
     Stats::Formula txBandwidth;
     Stats::Formula rxBandwidth;
     Stats::Formula txPacketRate;
     Stats::Formula rxPacketRate;
+    Stats::Scalar<> postedSwi;
+    Stats::Formula coalescedSwi;
+    Stats::Scalar<> totalSwi;
+    Stats::Scalar<> postedRxIdle;
+    Stats::Formula coalescedRxIdle;
+    Stats::Scalar<> totalRxIdle;
+    Stats::Scalar<> postedRxOk;
+    Stats::Formula coalescedRxOk;
+    Stats::Scalar<> totalRxOk;
+    Stats::Scalar<> postedRxDesc;
+    Stats::Formula coalescedRxDesc;
+    Stats::Scalar<> totalRxDesc;
+    Stats::Scalar<> postedTxOk;
+    Stats::Formula coalescedTxOk;
+    Stats::Scalar<> totalTxOk;
+    Stats::Scalar<> postedTxIdle;
+    Stats::Formula coalescedTxIdle;
+    Stats::Scalar<> totalTxIdle;
+    Stats::Scalar<> postedTxDesc;
+    Stats::Formula coalescedTxDesc;
+    Stats::Scalar<> totalTxDesc;
+    Stats::Scalar<> postedRxOrn;
+    Stats::Formula coalescedRxOrn;
+    Stats::Scalar<> totalRxOrn;
+    Stats::Formula coalescedTotal;
+    Stats::Scalar<> postedInterrupts;
+    Stats::Scalar<> droppedPackets;
 
   public:
     Tick cacheAccess(MemReqPtr &req);