Fix a small bug in parameter processing that would always result

[gem5.git] / dev / ns_gige.hh

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 9466e893004ec4a9c3560823d6d4bd64470048de..82f640db176b61dfd4f186c13443ee9d7ec01d2d 100644 (file)
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -34,20 +34,15 @@
 #ifndef __NS_GIGE_HH__
 #define __NS_GIGE_HH__
 
-//#include "base/range.hh"
+#include "base/statistics.hh"
 #include "dev/etherint.hh"
 #include "dev/etherpkt.hh"
-#include "sim/eventq.hh"
+#include "dev/io_device.hh"
 #include "dev/ns_gige_reg.h"
-#include "base/statistics.hh"
 #include "dev/pcidev.hh"
 #include "dev/tsunami.hh"
-#include "dev/io_device.hh"
 #include "mem/bus/bus.hh"
-
-/** defined by the NS83820 data sheet */
-#define MAX_TX_FIFO_SIZE 8192
-#define MAX_RX_FIFO_SIZE 32768
+#include "sim/eventq.hh"
 
 /** length of ethernet address in bytes */
 #define EADDR_LEN 6
@@ -91,7 +86,10 @@ struct dp_regs {
 };
 
 struct dp_rom {
-    /** for perfect match memory.  the linux driver doesn't use any other ROM */
+    /**
+     * for perfect match memory.
+     * the linux driver doesn't use any other ROM
+     */
     uint8_t perfectMatch[EADDR_LEN];
 };
 
@@ -158,21 +156,29 @@ class NSGigE : public PciDev
     dp_regs regs;
     dp_rom rom;
 
-     /*** BASIC STRUCTURES FOR TX/RX ***/
+    /** pci settings */
+    bool ioEnable;
+#if 0
+    bool memEnable;
+    bool bmEnable;
+#endif
+
+    /*** BASIC STRUCTURES FOR TX/RX ***/
     /* Data FIFOs */
     pktbuf_t txFifo;
+    uint32_t maxTxFifoSize;
     pktbuf_t rxFifo;
+    uint32_t maxRxFifoSize;
 
     /** various helper vars */
+    PacketPtr txPacket;
+    PacketPtr rxPacket;
     uint8_t *txPacketBufPtr;
     uint8_t *rxPacketBufPtr;
     uint32_t txXferLen;
     uint32_t rxXferLen;
-    uint32_t txPktXmitted;
     bool rxDmaFree;
     bool txDmaFree;
-    PacketPtr txPacket;
-    PacketPtr rxPacket;
 
     /** DescCaches */
     ns_desc txDescCache;
@@ -180,10 +186,10 @@ class NSGigE : public PciDev
 
     /* tx State Machine */
     TxState txState;
+    bool txEnable;
+
     /** Current Transmit Descriptor Done */
     bool CTDD;
-    /** amt of data in the txDataFifo in bytes (logical) */
-    uint32_t txFifoCnt;
     /** current amt of free space in txDataFifo in bytes */
     uint32_t txFifoAvail;
     /** halt the tx state machine after next packet */
@@ -196,6 +202,8 @@ class NSGigE : public PciDev
 
     /** rx State Machine */
     RxState rxState;
+    bool rxEnable;
+
     /** Current Receive Descriptor Done */
     bool CRDD;
     /** num of bytes in the current packet being drained from rxDataFifo */
@@ -261,18 +269,7 @@ class NSGigE : public PciDev
 
     void txReset();
     void rxReset();
-    void regsReset() {
-        memset(&regs, 0, sizeof(regs));
-        regs.config = 0x80000000;
-        regs.mear = 0x12;
-        regs.isr = 0x00608000;
-        regs.txcfg = 0x120;
-        regs.rxcfg = 0x4;
-        regs.srr = 0x0103;
-        regs.mibc = 0x2;
-        regs.vdr = 0x81;
-        regs.tesr = 0xc000;
-    }
+    void regsReset();
 
     void rxKick();
     Tick rxKickTick;
@@ -288,7 +285,13 @@ class NSGigE : public PciDev
      * Retransmit event
      */
     void transmit();
-    typedef EventWrapper<NSGigE, &NSGigE::transmit> TxEvent;
+    void txEventTransmit()
+    {
+        transmit();
+        if (txState == txFifoBlock)
+            txKick();
+    }
+    typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
     friend class TxEvent;
     TxEvent txEvent;
 
@@ -339,13 +342,14 @@ class NSGigE : public PciDev
 
   public:
     NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
-             PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
-             MemoryController *mmu, HierParams *hier, Bus *header_bus,
-             Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
-             bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
-             Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
-             PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
-             uint32_t func, bool rx_filter, const int eaddr[6]);
+           PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
+           MemoryController *mmu, HierParams *hier, Bus *header_bus,
+           Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
+           bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
+           Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
+           PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
+           uint32_t func, bool rx_filter, const int eaddr[6],
+           uint32_t tx_fifo_size, uint32_t rx_fifo_size);
     ~NSGigE();
 
     virtual void WriteConfig(int offset, int size, uint32_t data);
@@ -373,14 +377,19 @@ class NSGigE : public PciDev
     Stats::Scalar<> rxBytes;
     Stats::Scalar<> txPackets;
     Stats::Scalar<> rxPackets;
+    Stats::Scalar<> txIPChecksums;
+    Stats::Scalar<> rxIPChecksums;
+    Stats::Scalar<> txTCPChecksums;
+    Stats::Scalar<> rxTCPChecksums;
+    Stats::Scalar<> descDmaReads;
+    Stats::Scalar<> descDmaWrites;
+    Stats::Scalar<> descDmaRdBytes;
+    Stats::Scalar<> descDmaWrBytes;
     Stats::Formula txBandwidth;
     Stats::Formula rxBandwidth;
     Stats::Formula txPacketRate;
     Stats::Formula rxPacketRate;
 
-  private:
-    Tick pioLatency;
-
   public:
     Tick cacheAccess(MemReqPtr &req);
 };