* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* Device module for modelling the National Semiconductor
* DP83820 ethernet controller
*/
ns_desc txDescCache;
ns_desc rxDescCache;
+ /* state machine cycle time */
+ Tick clock;
+ inline Tick cycles(int numCycles) const { return numCycles * clock; }
+
/* tx State Machine */
TxState txState;
bool txEnable;
HierParams *hier;
Bus *header_bus;
Bus *payload_bus;
+ Tick clock;
Tick intr_delay;
Tick tx_delay;
Tick rx_delay;
Net::EthAddr eaddr;
uint32_t tx_fifo_size;
uint32_t rx_fifo_size;
+ uint32_t m5reg;
+ bool dma_no_allocate;
};
NSGigE(Params *params);
Stats::Scalar<> descDmaWrites;
Stats::Scalar<> descDmaRdBytes;
Stats::Scalar<> descDmaWrBytes;
+ Stats::Formula totBandwidth;
+ Stats::Formula totPackets;
+ Stats::Formula totBytes;
+ Stats::Formula totPacketRate;
Stats::Formula txBandwidth;
Stats::Formula rxBandwidth;
Stats::Formula txPacketRate;