* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* Device module for modelling the National Semiconductor
* DP83820 ethernet controller
*/
-#ifndef __NS_GIGE_HH__
-#define __NS_GIGE_HH__
+#ifndef __DEV_NS_GIGE_HH__
+#define __DEV_NS_GIGE_HH__
-//#include "base/range.hh"
+#include "base/inet.hh"
+#include "base/statistics.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
-#include "sim/eventq.hh"
+#include "dev/io_device.hh"
#include "dev/ns_gige_reg.h"
-#include "base/statistics.hh"
#include "dev/pcidev.hh"
-#include "dev/tsunami.hh"
-#include "dev/io_device.hh"
+#include "dev/pktfifo.hh"
#include "mem/bus/bus.hh"
-
-/** defined by the NS83820 data sheet */
-#define MAX_TX_FIFO_SIZE 8192
-#define MAX_RX_FIFO_SIZE 32768
-
-/** length of ethernet address in bytes */
-#define EADDR_LEN 6
+#include "sim/eventq.hh"
/**
* Ethernet device registers
};
struct dp_rom {
- /** for perfect match memory. the linux driver doesn't use any other ROM */
- uint8_t perfectMatch[EADDR_LEN];
+ /**
+ * for perfect match memory.
+ * the linux driver doesn't use any other ROM
+ */
+ uint8_t perfectMatch[ETH_ADDR_LEN];
};
-class IntrControl;
class NSGigEInt;
class PhysicalMemory;
class BaseInterface;
dmaWriteWaiting
};
- private:
- /** pointer to the chipset */
- Tsunami *tsunami;
-
private:
Addr addr;
static const Addr size = sizeof(dp_regs);
/*** BASIC STRUCTURES FOR TX/RX ***/
/* Data FIFOs */
- pktbuf_t txFifo;
- pktbuf_t rxFifo;
+ PacketFifo txFifo;
+ PacketFifo rxFifo;
/** various helper vars */
PacketPtr txPacket;
ns_desc txDescCache;
ns_desc rxDescCache;
+ /* state machine cycle time */
+ Tick clock;
+ inline Tick cycles(int numCycles) const { return numCycles * clock; }
+
/* tx State Machine */
TxState txState;
+ bool txEnable;
+
/** Current Transmit Descriptor Done */
bool CTDD;
- /** current amt of free space in txDataFifo in bytes */
- uint32_t txFifoAvail;
/** halt the tx state machine after next packet */
bool txHalt;
/** ptr to the next byte in the current fragment */
/** rx State Machine */
RxState rxState;
+ bool rxEnable;
+
/** Current Receive Descriptor Done */
bool CRDD;
/** num of bytes in the current packet being drained from rxDataFifo */
uint32_t rxPktBytes;
- /** number of bytes in the rxFifo */
- uint32_t rxFifoCnt;
/** halt the rx state machine after current packet */
bool rxHalt;
/** ptr to the next byte in current fragment */
void rxKick();
Tick rxKickTick;
typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
- friend class RxKickEvent;
+ friend void RxKickEvent::process();
void txKick();
Tick txKickTick;
typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
- friend class TxKickEvent;
+ friend void TxKickEvent::process();
/**
* Retransmit event
*/
void transmit();
- typedef EventWrapper<NSGigE, &NSGigE::transmit> TxEvent;
- friend class TxEvent;
+ void txEventTransmit()
+ {
+ transmit();
+ if (txState == txFifoBlock)
+ txKick();
+ }
+ typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
+ friend void TxEvent::process();
TxEvent txEvent;
void txDump() const;
* receive address filter
*/
bool rxFilterEnable;
- bool rxFilter(PacketPtr packet);
+ bool rxFilter(const PacketPtr &packet);
bool acceptBroadcast;
bool acceptMulticast;
bool acceptUnicast;
/**
* Interrupt management
*/
- IntrControl *intctrl;
void devIntrPost(uint32_t interrupts);
void devIntrClear(uint32_t interrupts);
void devIntrChangeMask();
void cpuIntrClear();
typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
- friend class IntrEvent;
+ friend void IntrEvent::process();
IntrEvent *intrEvent;
-
- /**
- * Hardware checksum support
- */
- bool udpChecksum(PacketPtr packet, bool gen);
- bool tcpChecksum(PacketPtr packet, bool gen);
- bool ipChecksum(PacketPtr packet, bool gen);
- uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len);
-
NSGigEInt *interface;
public:
- NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
- PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
- MemoryController *mmu, HierParams *hier, Bus *header_bus,
- Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
- bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
- Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
- PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
- uint32_t func, bool rx_filter, const int eaddr[6]);
+ struct Params : public PciDev::Params
+ {
+ PhysicalMemory *pmem;
+ HierParams *hier;
+ Bus *header_bus;
+ Bus *payload_bus;
+ Tick clock;
+ Tick intr_delay;
+ Tick tx_delay;
+ Tick rx_delay;
+ Tick pio_latency;
+ bool dma_desc_free;
+ bool dma_data_free;
+ Tick dma_read_delay;
+ Tick dma_write_delay;
+ Tick dma_read_factor;
+ Tick dma_write_factor;
+ bool rx_filter;
+ Net::EthAddr eaddr;
+ uint32_t tx_fifo_size;
+ uint32_t rx_fifo_size;
+ uint32_t m5reg;
+ bool dma_no_allocate;
+ };
+
+ NSGigE(Params *params);
~NSGigE();
+ const Params *params() const { return (const Params *)_params; }
virtual void WriteConfig(int offset, int size, uint32_t data);
virtual void ReadConfig(int offset, int size, uint8_t *data);
Stats::Scalar<> rxBytes;
Stats::Scalar<> txPackets;
Stats::Scalar<> rxPackets;
+ Stats::Scalar<> txIpChecksums;
+ Stats::Scalar<> rxIpChecksums;
+ Stats::Scalar<> txTcpChecksums;
+ Stats::Scalar<> rxTcpChecksums;
+ Stats::Scalar<> txUdpChecksums;
+ Stats::Scalar<> rxUdpChecksums;
+ Stats::Scalar<> descDmaReads;
+ Stats::Scalar<> descDmaWrites;
+ Stats::Scalar<> descDmaRdBytes;
+ Stats::Scalar<> descDmaWrBytes;
+ Stats::Formula totBandwidth;
+ Stats::Formula totPackets;
+ Stats::Formula totBytes;
+ Stats::Formula totPacketRate;
Stats::Formula txBandwidth;
Stats::Formula rxBandwidth;
Stats::Formula txPacketRate;
Stats::Formula rxPacketRate;
-
- private:
- Tick pioLatency;
+ Stats::Scalar<> postedSwi;
+ Stats::Formula coalescedSwi;
+ Stats::Scalar<> totalSwi;
+ Stats::Scalar<> postedRxIdle;
+ Stats::Formula coalescedRxIdle;
+ Stats::Scalar<> totalRxIdle;
+ Stats::Scalar<> postedRxOk;
+ Stats::Formula coalescedRxOk;
+ Stats::Scalar<> totalRxOk;
+ Stats::Scalar<> postedRxDesc;
+ Stats::Formula coalescedRxDesc;
+ Stats::Scalar<> totalRxDesc;
+ Stats::Scalar<> postedTxOk;
+ Stats::Formula coalescedTxOk;
+ Stats::Scalar<> totalTxOk;
+ Stats::Scalar<> postedTxIdle;
+ Stats::Formula coalescedTxIdle;
+ Stats::Scalar<> totalTxIdle;
+ Stats::Scalar<> postedTxDesc;
+ Stats::Formula coalescedTxDesc;
+ Stats::Scalar<> totalTxDesc;
+ Stats::Scalar<> postedRxOrn;
+ Stats::Formula coalescedRxOrn;
+ Stats::Scalar<> totalRxOrn;
+ Stats::Formula coalescedTotal;
+ Stats::Scalar<> postedInterrupts;
+ Stats::Scalar<> droppedPackets;
public:
Tick cacheAccess(MemReqPtr &req);
NSGigEInt(const std::string &name, NSGigE *d)
: EtherInt(name), dev(d) { dev->setInterface(this); }
- virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); }
+ virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
virtual void sendDone() { dev->transferDone(); }
};
-#endif // __NS_GIGE_HH__
+#endif // __DEV_NS_GIGE_HH__
projects / gem5.git / blobdiff