split uart into urt8250 and uart8530

[gem5.git] / dev / ns_gige.hh

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 58060edacf2e1b640e3cd29c68a82d3a869be820..a1e90a375bb59c342d2181aceb3332f225462171 100644 (file)
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Device module for modelling the National Semiconductor
  * DP83820 ethernet controller
  */
@@ -175,6 +175,10 @@ class NSGigE : public PciDev
     ns_desc txDescCache;
     ns_desc rxDescCache;
 
+    /* state machine cycle time */
+    Tick clock;
+    inline Tick cycles(int numCycles) const { return numCycles * clock; }
+
     /* tx State Machine */
     TxState txState;
     bool txEnable;
@@ -324,6 +328,7 @@ class NSGigE : public PciDev
         HierParams *hier;
         Bus *header_bus;
         Bus *payload_bus;
+        Tick clock;
         Tick intr_delay;
         Tick tx_delay;
         Tick rx_delay;
@@ -338,6 +343,8 @@ class NSGigE : public PciDev
         Net::EthAddr eaddr;
         uint32_t tx_fifo_size;
         uint32_t rx_fifo_size;
+        uint32_t m5reg;
+        bool dma_no_allocate;
     };
 
     NSGigE(Params *params);