* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* Device module for modelling the National Semiconductor
* DP83820 ethernet controller
*/
uint8_t perfectMatch[ETH_ADDR_LEN];
};
-class IntrControl;
class NSGigEInt;
class PhysicalMemory;
class BaseInterface;
ns_desc txDescCache;
ns_desc rxDescCache;
+ /* state machine cycle time */
+ Tick clock;
+ inline Tick cycles(int numCycles) const { return numCycles * clock; }
+
/* tx State Machine */
TxState txState;
bool txEnable;
void rxKick();
Tick rxKickTick;
typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
- friend class RxKickEvent;
+ friend void RxKickEvent::process();
void txKick();
Tick txKickTick;
typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
- friend class TxKickEvent;
+ friend void TxKickEvent::process();
/**
* Retransmit event
txKick();
}
typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
- friend class TxEvent;
+ friend void TxEvent::process();
TxEvent txEvent;
void txDump() const;
/**
* Interrupt management
*/
- IntrControl *intctrl;
void devIntrPost(uint32_t interrupts);
void devIntrClear(uint32_t interrupts);
void devIntrChangeMask();
void cpuIntrClear();
typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
- friend class IntrEvent;
+ friend void IntrEvent::process();
IntrEvent *intrEvent;
NSGigEInt *interface;
HierParams *hier;
Bus *header_bus;
Bus *payload_bus;
+ Tick clock;
Tick intr_delay;
Tick tx_delay;
Tick rx_delay;
Net::EthAddr eaddr;
uint32_t tx_fifo_size;
uint32_t rx_fifo_size;
+ uint32_t m5reg;
+ bool dma_no_allocate;
};
NSGigE(Params *params);
Stats::Scalar<> descDmaWrites;
Stats::Scalar<> descDmaRdBytes;
Stats::Scalar<> descDmaWrBytes;
+ Stats::Formula totBandwidth;
+ Stats::Formula totPackets;
+ Stats::Formula totBytes;
+ Stats::Formula totPacketRate;
Stats::Formula txBandwidth;
Stats::Formula rxBandwidth;
Stats::Formula txPacketRate;
Stats::Formula rxPacketRate;
+ Stats::Scalar<> postedSwi;
+ Stats::Formula coalescedSwi;
+ Stats::Scalar<> totalSwi;
+ Stats::Scalar<> postedRxIdle;
+ Stats::Formula coalescedRxIdle;
+ Stats::Scalar<> totalRxIdle;
+ Stats::Scalar<> postedRxOk;
+ Stats::Formula coalescedRxOk;
+ Stats::Scalar<> totalRxOk;
+ Stats::Scalar<> postedRxDesc;
+ Stats::Formula coalescedRxDesc;
+ Stats::Scalar<> totalRxDesc;
+ Stats::Scalar<> postedTxOk;
+ Stats::Formula coalescedTxOk;
+ Stats::Scalar<> totalTxOk;
+ Stats::Scalar<> postedTxIdle;
+ Stats::Formula coalescedTxIdle;
+ Stats::Scalar<> totalTxIdle;
+ Stats::Scalar<> postedTxDesc;
+ Stats::Formula coalescedTxDesc;
+ Stats::Scalar<> totalTxDesc;
+ Stats::Scalar<> postedRxOrn;
+ Stats::Formula coalescedRxOrn;
+ Stats::Scalar<> totalRxOrn;
+ Stats::Formula coalescedTotal;
+ Stats::Scalar<> postedInterrupts;
+ Stats::Scalar<> droppedPackets;
public:
Tick cacheAccess(MemReqPtr &req);