dp_rom rom;
/** pci settings */
- bool io_enable;
+ bool ioEnable;
#if 0
- bool mem_enable;
- bool bm_enable;
+ bool memEnable;
+ bool bmEnable;
#endif
/*** BASIC STRUCTURES FOR TX/RX ***/
uint8_t *rxPacketBufPtr;
uint32_t txXferLen;
uint32_t rxXferLen;
- uint32_t txPktXmitted;
bool rxDmaFree;
bool txDmaFree;
TxState txState;
/** Current Transmit Descriptor Done */
bool CTDD;
- /** amt of data in the txDataFifo in bytes (logical) */
- uint32_t txFifoCnt;
/** current amt of free space in txDataFifo in bytes */
uint32_t txFifoAvail;
/** halt the tx state machine after next packet */
Stats::Scalar<> rxBytes;
Stats::Scalar<> txPackets;
Stats::Scalar<> rxPackets;
+ Stats::Scalar<> txIPChecksums;
+ Stats::Scalar<> rxIPChecksums;
+ Stats::Scalar<> txTCPChecksums;
+ Stats::Scalar<> rxTCPChecksums;
+ Stats::Scalar<> descDmaReads;
+ Stats::Scalar<> descDmaWrites;
+ Stats::Scalar<> descDmaRdBytes;
+ Stats::Scalar<> descDmaWrBytes;
Stats::Formula txBandwidth;
Stats::Formula rxBandwidth;
Stats::Formula txPacketRate;