store the checkpoint to the proper directory

[gem5.git] / dev / ns_gige.hh

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index cb65507205f9baba0d7fe3d90b87251f718e5eac..a8d8d1f18dac194b06cd0f2220b019038b770471 100644 (file)
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -96,7 +96,7 @@ struct dp_rom {
 };
 
 class IntrControl;
-class EtherDevInt;
+class NSGigEInt;
 class PhysicalMemory;
 class BaseInterface;
 class HierParams;
@@ -106,7 +106,7 @@ class PciConfigAll;
 /**
  * NS DP82830 Ethernet device model
  */
-class EtherDev : public PciDev
+class NSGigE : public PciDev
 {
   public:
     /** Transmit State Machine states */
@@ -158,21 +158,27 @@ class EtherDev : public PciDev
     dp_regs regs;
     dp_rom rom;
 
-     /*** BASIC STRUCTURES FOR TX/RX ***/
+    /** pci settings */
+    bool ioEnable;
+#if 0
+    bool memEnable;
+    bool bmEnable;
+#endif
+
+    /*** BASIC STRUCTURES FOR TX/RX ***/
     /* Data FIFOs */
     pktbuf_t txFifo;
     pktbuf_t rxFifo;
 
     /** various helper vars */
+    PacketPtr txPacket;
+    PacketPtr rxPacket;
     uint8_t *txPacketBufPtr;
     uint8_t *rxPacketBufPtr;
     uint32_t txXferLen;
     uint32_t rxXferLen;
-    uint32_t txPktXmitted;
     bool rxDmaFree;
     bool txDmaFree;
-    PacketPtr txPacket;
-    PacketPtr rxPacket;
 
     /** DescCaches */
     ns_desc txDescCache;
@@ -182,8 +188,6 @@ class EtherDev : public PciDev
     TxState txState;
     /** Current Transmit Descriptor Done */
     bool CTDD;
-    /** amt of data in the txDataFifo in bytes (logical) */
-    uint32_t txFifoCnt;
     /** current amt of free space in txDataFifo in bytes */
     uint32_t txFifoAvail;
     /** halt the tx state machine after next packet */
@@ -236,20 +240,20 @@ class EtherDev : public PciDev
     void  txDmaWriteCopy();
 
     void rxDmaReadDone();
-    friend class EventWrapper<EtherDev, &EtherDev::rxDmaReadDone>;
-    EventWrapper<EtherDev, &EtherDev::rxDmaReadDone> rxDmaReadEvent;
+    friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
+    EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
 
     void rxDmaWriteDone();
-    friend class EventWrapper<EtherDev, &EtherDev::rxDmaWriteDone>;
-    EventWrapper<EtherDev, &EtherDev::rxDmaWriteDone> rxDmaWriteEvent;
+    friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
+    EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
 
     void txDmaReadDone();
-    friend class EventWrapper<EtherDev, &EtherDev::txDmaReadDone>;
-    EventWrapper<EtherDev, &EtherDev::txDmaReadDone> txDmaReadEvent;
+    friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
+    EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
 
     void txDmaWriteDone();
-    friend class EventWrapper<EtherDev, &EtherDev::txDmaWriteDone>;
-    EventWrapper<EtherDev, &EtherDev::txDmaWriteDone> txDmaWriteEvent;
+    friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
+    EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
 
     bool dmaDescFree;
     bool dmaDataFree;
@@ -261,34 +265,23 @@ class EtherDev : public PciDev
 
     void txReset();
     void rxReset();
-    void regsReset() {
-        memset(&regs, 0, sizeof(regs));
-        regs.config = 0x80000000;
-        regs.mear = 0x12;
-        regs.isr = 0x00608000;
-        regs.txcfg = 0x120;
-        regs.rxcfg = 0x4;
-        regs.srr = 0x0103;
-        regs.mibc = 0x2;
-        regs.vdr = 0x81;
-        regs.tesr = 0xc000;
-    }
+    void regsReset();
 
     void rxKick();
     Tick rxKickTick;
-    typedef EventWrapper<EtherDev, &EtherDev::rxKick> RxKickEvent;
+    typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
     friend class RxKickEvent;
 
     void txKick();
     Tick txKickTick;
-    typedef EventWrapper<EtherDev, &EtherDev::txKick> TxKickEvent;
+    typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
     friend class TxKickEvent;
 
     /**
      * Retransmit event
      */
     void transmit();
-    typedef EventWrapper<EtherDev, &EtherDev::transmit> TxEvent;
+    typedef EventWrapper<NSGigE, &NSGigE::transmit> TxEvent;
     friend class TxEvent;
     TxEvent txEvent;
 
@@ -323,7 +316,7 @@ class EtherDev : public PciDev
     void cpuInterrupt();
     void cpuIntrClear();
 
-    typedef EventWrapper<EtherDev, &EtherDev::cpuInterrupt> IntrEvent;
+    typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
     friend class IntrEvent;
     IntrEvent *intrEvent;
 
@@ -335,18 +328,18 @@ class EtherDev : public PciDev
     bool ipChecksum(PacketPtr packet, bool gen);
     uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len);
 
-    EtherDevInt *interface;
+    NSGigEInt *interface;
 
   public:
-    EtherDev(const std::string &name, IntrControl *i, Tick intr_delay,
+    NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
              PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
              MemoryController *mmu, HierParams *hier, Bus *header_bus,
              Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
              bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
              Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
              PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
-             uint32_t func, bool rx_filter, const int eaddr[6], Addr addr);
-    ~EtherDev();
+             uint32_t func, bool rx_filter, const int eaddr[6]);
+    ~NSGigE();
 
     virtual void WriteConfig(int offset, int size, uint32_t data);
     virtual void ReadConfig(int offset, int size, uint8_t *data);
@@ -360,7 +353,7 @@ class EtherDev : public PciDev
     bool recvPacket(PacketPtr packet);
     void transferDone();
 
-    void setInterface(EtherDevInt *i) { assert(!interface); interface = i; }
+    void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
 
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
@@ -369,14 +362,22 @@ class EtherDev : public PciDev
     void regStats();
 
   private:
-    Statistics::Scalar<> txBytes;
-    Statistics::Scalar<> rxBytes;
-    Statistics::Scalar<> txPackets;
-    Statistics::Scalar<> rxPackets;
-    Statistics::Formula txBandwidth;
-    Statistics::Formula rxBandwidth;
-    Statistics::Formula txPacketRate;
-    Statistics::Formula rxPacketRate;
+    Stats::Scalar<> txBytes;
+    Stats::Scalar<> rxBytes;
+    Stats::Scalar<> txPackets;
+    Stats::Scalar<> rxPackets;
+    Stats::Scalar<> txIPChecksums;
+    Stats::Scalar<> rxIPChecksums;
+    Stats::Scalar<> txTCPChecksums;
+    Stats::Scalar<> rxTCPChecksums;
+    Stats::Scalar<> descDmaReads;
+    Stats::Scalar<> descDmaWrites;
+    Stats::Scalar<> descDmaRdBytes;
+    Stats::Scalar<> descDmaWrBytes;
+    Stats::Formula txBandwidth;
+    Stats::Formula rxBandwidth;
+    Stats::Formula txPacketRate;
+    Stats::Formula rxPacketRate;
 
   private:
     Tick pioLatency;
@@ -388,13 +389,13 @@ class EtherDev : public PciDev
 /*
  * Ethernet Interface for an Ethernet Device
  */
-class EtherDevInt : public EtherInt
+class NSGigEInt : public EtherInt
 {
   private:
-    EtherDev *dev;
+    NSGigE *dev;
 
   public:
-    EtherDevInt(const std::string &name, EtherDev *d)
+    NSGigEInt(const std::string &name, NSGigE *d)
         : EtherInt(name), dev(d) { dev->setInterface(this); }
 
     virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); }